From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 571F045F32; Tue, 24 Dec 2024 22:57:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3D4834029D; Tue, 24 Dec 2024 22:57:58 +0100 (CET) Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) by mails.dpdk.org (Postfix) with ESMTP id 1153640263 for ; Tue, 24 Dec 2024 22:57:57 +0100 (CET) Received: by mail-pj1-f48.google.com with SMTP id 98e67ed59e1d1-2eec9b3a1bbso4459719a91.3 for ; Tue, 24 Dec 2024 13:57:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; t=1735077476; x=1735682276; darn=dpdk.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=EENfmCnwwFUa9AGmDfAJgHxhx2HrFtyIfqV9puE45e4=; b=U/fCKL6Cddowa2lBucW4OWnOoEhoTakT6LM0p841sI/9VJhwEL2EqfoidVuVG+JFtM y2tHvZLGKGQuQOnYojDnsCPswmDecth/fZC81vciSnUiZVJD9CedSOJck7g4YVyyb7f/ NvLZHUh/ej2oqkMo/HbpU8AIAtHvMZ2jbPKCg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735077476; x=1735682276; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=EENfmCnwwFUa9AGmDfAJgHxhx2HrFtyIfqV9puE45e4=; b=H23KUzNkh6M+S3sjnHERQUhWPGaS9G7ezeKPrcdzNB0v9cFawEtEh67ngdWiFZ2EOO 9CJyxQewML+NlJ+idDpb+TTz2w/Ey5zoOCaGG19QXJB6SeCl5wURxLwcUBGwryB3aRVn h2W+QfBXNxLUoqKfzefrHJ/oNcMS8TNSxtkuNboaqtR5T6l6L3e/3C4WrdtRYA+6Ex3B 0JoazzKnQNRLpkAnCzTs3zHzTaD0lwhRfqpWOV1UDXVNB/rzFSWEAxURZOH7T/DdWXPT By8f0xf3lf5zDk614Z6c1yn9Vr4WGA4z4hFenKdg3yfpdeT2XpKS//566BZC7jscB74y ylvw== X-Forwarded-Encrypted: i=1; AJvYcCUviNq1oN2JnU9GS5mxGELhIUjrGmTxtnN9QxLCKTxXL9jSnPlFf0xxaqy2e0CjqloJvg==@dpdk.org X-Gm-Message-State: AOJu0YzhkH4TCW3l83MkXYQL5aFcndm4sjeq6Kab094aMj+OimYxy6qv mBJrSNVAqd3n8eWbOfopB0Rs7OYhWrVSdmh0AgdjfkOkgJ22MquELYrYAsvvYAp6xzlfWh5B0VT CsBrxqJdOWZtCF6tQ97ZRXpPuZIhavU29I5OCtQ== X-Gm-Gg: ASbGncsXZ0GjocFXfGKvX5DP4fIkHbqpgXrb4PqiFF2GYOjKss2TxO4A6T5Pon68ZUf IRA/OuMwOFfy/3S16uHTAd2qIif4kyq5Yc0NQ23c/F1l9VTHOqfWVDK19upj1HdI8tI0ITLk= X-Google-Smtp-Source: AGHT+IE0s18qZk9bzs7zOGGo7oGm7s5AA/6rY6YxBXu09/AzETqkcgNAYOotlWA9UxbJkhbOJPq0bja2BOqm1wTs/hs= X-Received: by 2002:a17:90b:2d88:b0:2ee:af31:a7bd with SMTP id 98e67ed59e1d1-2f452def1d1mr29025650a91.5.1735077475959; Tue, 24 Dec 2024 13:57:55 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Patrick Robb Date: Tue, 24 Dec 2024 16:55:24 -0500 Message-ID: Subject: Re: [EXTERNAL] CN10K Crypto Test Issue To: Bharath Rajendra Cc: Vivek Garg , JogaRao Nartu , Hiral Shah , Cody Cheng , Gnanesh Kambalu Palanethra , "ci@dpdk.org" , Akhil Goyal , Jerin Jacob , Anoob Joseph Content-Type: multipart/alternative; boundary="0000000000009cddfb062a0b3442" X-BeenThere: ci@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK CI discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: ci-bounces@dpdk.org --0000000000009cddfb062a0b3442 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Bharath, Apologies for my delay in response. That's strange that it is working on your system. Thank you for testing this, and thanks again for meeting the other day. I do not see any difference in our bootargs which is likely to cause this cryptodev issue. If the binary dpdk-test that our native build is producing is valid (since it worked on your system), and we are using the same hardware (I think we are both on cn10k), then perhaps the software environment is to blame. Since we just flashed firmware and built the latest SDK, I don't think that is an issue but we can re-do it if you think it makes sense. One thing I can do is re-do the setup of the SDK kernel + ubuntu rootfs, on a separate partition, boot to that environment and attempt to use the dpdk-test binary there. What I will use for this process is the "Booting to Ubuntu rootfs using Velox SDK kernel" from doc-base-SDK12.24.11/kernel/ubuntu_rootfs.html. Someone else on our team did this before, and although I believe he did it all according to the docs, it doesn't hurt to run through it again to make sure. Any other troubleshooting ideas are welcome, if you have any! Also, since Marvell is a member of our lab, as always I can grant VPN access to anyone if they want to poke around this system! =3DI am on vacation for the next two weeks for winter holidays, but I will make sure to work on this ASAP when I'm back and report back to you all what happened. Thanks and happy holidays. -Patrick On Thu, Dec 19, 2024 at 8:35=E2=80=AFAM Anoob Joseph w= rote: > Hi Vivek, > > > > We do not support these cases. The opcodes are optimized for PDCP use cas= e > and in the internal branch we have these tests disabled. > > > > Thanks, > > Anoob > > > > *From:* Vivek Garg > *Sent:* Thursday, December 19, 2024 6:18 PM > *To:* JogaRao Nartu ; Bharath Rajendra < > brajendra@marvell.com>; Patrick Robb ; Hiral Shah < > hshah@marvell.com>; Anoob Joseph > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; ci@dpdk.org; Akhil Goyal ; > Anoob Joseph ; Jerin Jacob > *Subject:* RE: [EXTERNAL] CN10K Crypto Test Issue > > > > HI Anoob, > > Below Jira created for snow 3G Test Failures in cryptodev_cn10k_autotest > tests on 106 with native build binary. > > [IPBUSW-58120] SNOW 3G Test Suite are failing in cryptodev_cn10k_autotest > tests on 106 with native build binary. - Marvell Jira Production System > > > > > Thanks, > > Vivek > > > > > > *From:* JogaRao Nartu > *Sent:* Thursday, December 19, 2024 5:46 PM > *To:* Bharath Rajendra ; Patrick Robb < > probb@iol.unh.edu>; Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; ci@dpdk.org; Akhil Goyal ; > Vivek Garg ; Anoob Joseph ; Jerin > Jacob > *Subject:* RE: [EXTERNAL] CN10K Crypto Test Issue > > > > ++ > > > > *From:* Bharath Rajendra > *Sent:* Thursday, December 19, 2024 5:44 PM > *To:* Patrick Robb ; Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; JogaRao Nartu ; > ci@dpdk.org; Akhil Goyal ; Vivek Garg < > vgarg@marvell.com> > *Subject:* RE: [EXTERNAL] CN10K Crypto Test Issue > > > > Hi Patrick, > > > > We followed the instructions which you used and also the application whic= h > you shared over email. > > On our setup it is working as expected. Attached the complete logs for th= e > reference. > > > > Bootargs: > > console=3DttyAMA0,115200n8 earlycon=3Dpl011,0x87e028000000 maxcpus=3D24 r= ootwait > rw root=3D/dev/nfs nfsroot=3D10.29.56.91:/srv/tftp/regression-debug-2980-= db-cn106xx-crb-b0-cisco-267/dut/rootfs,v3,tcp > ip=3Ddhcp coherent_pool=3D16M default_hugepagesz=3D512M hugepagesz=3D512M > hugepages=3D8 > > > > *Enabling CPT VF=E2=80=99s:* > > # echo 1 > /sys/bus/pci/devices/0002:20:00.0/sriov_numvfs > > #/usr/bin/dpdk-devbind.py -b vfio-pci 0002:20:00.1 > > *Setting up huge pages:* > > #mkdir -p /mnt/huge > > #mount -t hugetlbfs nodev /mnt/huge > > > > Note: cryptodev_cn10k_asymautotest works without any issues. But with > cryptodev_cn10k_autotest observed few test failure, this we will track > internally with dev team. But we are not observing =E2=80=9Crequest timeo= ut error=E2=80=9D > > > > Regards > > Bharath Rajendra > > > > *From:* Patrick Robb > *Sent:* Thursday, December 19, 2024 12:29 AM > *To:* Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; JogaRao Nartu ; Bharath > Rajendra ; ci@dpdk.org; Akhil Goyal < > gakhil@marvell.com> > *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue > > > > Hi Bharath and others, Here is the download link to the dpdk-test produce= d > with the native compile on the cn10k host: https: //drive. google. > com/file/d/127sIjCok3ErxAjrvfncWbv7BOmgL8m6D/view?usp=3Dsharing Thanks, > looking forward to hearing back > > Hi Bharath and others, > > > > Here is the download link to the dpdk-test produced with the native > compile on the cn10k host: > https://drive.google.com/file/d/127sIjCok3ErxAjrvfncWbv7BOmgL8m6D/view?us= p=3Dsharing > > > > > Thanks, looking forward to hearing back from you about how a native build > works on your setup. And, apologies for the late meeting time for you - I > did not realize which time zone you were in. If it turns out that a > followup meeting is required I will be sure to schedule it earlier in the > day. > > > > I'm also adding the DPDK crypto tree maintainer (Akhil Goyal) to the CC > list for this thread. > > > > Best, > > Patrick > > > > On Wed, Dec 18, 2024 at 12:53=E2=80=AFPM Hiral Shah w= rote: > > > > Looks like meeting is over. > > > > Thanks Bharath! > > > > Regards, > > Hiral > ------------------------------ > > *From:* Patrick Robb > *Sent:* Wednesday, December 18, 2024 9:45 AM > *To:* Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; JogaRao Nartu ; Bharath > Rajendra ; ci@dpdk.org > *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue > > > > No worries, Bharath and the others are demonstrating the driver binding > and autotest procedure. On Wed, Dec 18, 2024 at 12: 37 PM Hiral Shah marvell. com> wrote: Hi Cody, Patrick, Give me 10 -15 more meeting. I am = on > another call. > > No worries, Bharath and the others are demonstrating the driver binding > and autotest procedure. > > > > On Wed, Dec 18, 2024 at 12:37=E2=80=AFPM Hiral Shah w= rote: > > Hi Cody, Patrick, > > > > Give me 10 -15 more meeting. I am on another call. > > > > > > Regards, > > Hiral > ------------------------------ > > *From:* Patrick Robb > *Sent:* Monday, December 16, 2024 1:57 PM > *To:* Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; JogaRao Nartu ; Bharath > Rajendra ; ci@dpdk.org > *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue > > > > Hi Hiral, Sorry about the last minute planning today - I am scheduling a > call for us for Wednesday at 9: 30AM PST. Cody will be in class at that > time but I will be available and I believe I know all the details of his > issue. > -------------------------------------------------------------------------= ---------------------------------- > > Hi Hiral, > > > > Sorry about the last minute planning today - I am scheduling a call for u= s > for Wednesday at 9:30AM PST. Cody will be in class at that time but I wil= l > be available and I believe I know all the details of his issue. > > > > > -------------------------------------------------------------------------= ---------------------------------- > > > > Patrick Robb is inviting you to a scheduled Zoom meeting. > > Topic: Marvell Crypto Sync > Time: Dec 18, 2024 12:30 PM Eastern Time (US and Canada) > > Join from PC, Mac, Linux, iOS or Android: > https://unh.zoom.us/j/93859170209 > > > Keyboard shortcuts are available to navigate this Zoom meeting or webinar= : > https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard= -for-Zoom > > > Or iPhone one-tap: 13052241968,93859170209# or 13092053325,93859170209# > > Or Telephone: > Dial: +1 305 224 1968 (US Toll) > Meeting ID: 938 5917 0209 > International numbers available: https://unh.zoom.us/u/acTtiNQKou > > > Or a H.323/SIP room system: > H.323: rc.unh.edu > > or 144.195.19.161 (US West) or 206.247.11.121 (US East) > Meeting ID: 938 5917 0209 > SIP: 93859170209@zoomcrc.com > > TROUBLESHOOTING STEPS: > > Audio Echo In A Meeting: > https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeti= ng > > > Want to Join a Test Meeting?: https://zoom.us/test > > > > > On Mon, Dec 16, 2024 at 3:51=E2=80=AFPM Patrick Robb = wrote: > > Thanks Hiral for the offer of help, here is a zoom invite for a meeting > from 1pm-2pm PST today (in 10 minutes). > > > > Sorry for the last notice, I can certainly reschedule if needed. > > > > Patrick Robb is inviting you to a scheduled Zoom meeting. > > Topic: Marvell DPDK Cryptodev sync > Time: Dec 16, 2024 04:00 PM Eastern Time (US and Canada) > > Join from PC, Mac, Linux, iOS or Android: > https://unh.zoom.us/j/99749831096 > > > Keyboard shortcuts are available to navigate this Zoom meeting or webinar= : > https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard= -for-Zoom > > > Or iPhone one-tap: 16468769923,99749831096# or 16469313860,99749831096# > > Or Telephone: > Dial: +1 646 876 9923 (US Toll) > Meeting ID: 997 4983 1096 > International numbers available: https://unh.zoom.us/u/aAZFiJCIr > > > Or a H.323/SIP room system: > H.323: rc.unh.edu > > or 144.195.19.161 (US West) or 206.247.11.121 (US East) > Meeting ID: 997 4983 1096 > SIP: 99749831096@zoomcrc.com > > TROUBLESHOOTING STEPS: > > Audio Echo In A Meeting: > https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeti= ng > > > Want to Join a Test Meeting?: https://zoom.us/test > > > > > On Mon, Dec 16, 2024 at 2:39=E2=80=AFPM Patrick Robb = wrote: > > Thanks, just confirming is this pacific time? > > > > On Mon, Dec 16, 2024 at 2:27=E2=80=AFPM Hiral Shah wr= ote: > > Sure! > > > > We can have sync up today between 1PM -3 PM or Wednesday 8:30AM -1 PM. > > > > > > Regards, > > Hiral > ------------------------------ > > *From:* Patrick Robb > *Sent:* Monday, December 16, 2024 10:55 AM > *To:* Hiral Shah > *Cc:* Cody Cheng ; Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com>; JogaRao Nartu ; Bharath > Rajendra ; ci@dpdk.org > *Subject:* Re: [EXTERNAL] CN10K Crypto Test Issue > > > > Hi Hiral, The cnxk crypto device VF creation and driver binding steps tha= t > Cody wrote in his email are actually straight from the SDK document. > Specifically he followed the steps from doc-base-SDK12. 24. > 11/dpdk/pmd/rte_cryptodev. html#initialization > > Hi Hiral, > > > > The cnxk crypto device VF creation and driver binding steps that Cody > wrote in his email are actually straight from the SDK document. > Specifically he followed the steps > from doc-base-SDK12.24.11/dpdk/pmd/rte_cryptodev.html#initialization > > > > Thanks for offering a sync up - this would be ideal as we are still stuck= . > We can schedule a Zoom and invite you. Do I remember correctly that you a= re > in the pacific time zone? Is any particular day this week good for you? > > > > Thanks for all the help. > > -Patrick > > > > On Mon, Dec 16, 2024 at 1:33=E2=80=AFPM Hiral Shah wr= ote: > > Hi Cody, > > > > Can you please refer our SDK document? It should have clear instructions. > We can sync up if you still have any questions. > > > > Regards, > > Hiral > ------------------------------ > > *From:* Cody Cheng > *Sent:* Friday, December 13, 2024 11:47 AM > *To:* Gnanesh Kambalu Palanethra ; Hiral Shah < > hshah@marvell.com> > *Cc:* JogaRao Nartu ; Bharath Rajendra < > brajendra@marvell.com>; Patrick Robb ; ci@dpdk.org < > ci@dpdk.org> > *Subject:* [EXTERNAL] CN10K Crypto Test Issue > > > > Hi Gnanesh & Hiral, My name is Cody Cheng, I'm a tester at the University > of New Hampshire DPDK Community Test Lab. We are hosting a CN10K board he= re > which is currently running some ethernet device tests on DPDK, and we wou= ld > like to extend > > Hi Gnanesh & Hiral, > > > > My name is Cody Cheng, I'm a tester at the University of New Hampshire > > DPDK Community Test Lab. We are hosting a CN10K board here which is > > currently running some ethernet device tests on DPDK, and we would > > like to extend our testing to include crypto device testing. Gnanesh > > has written a patch which adds testcases to the DPDK Test Suite which > > should allow us to do so. > > > > However, I am running into difficulties with the crypto devices I > > create in DPDK from the CN10K board. I would appreciate it if I can > > sync with one of you next week so that I can show our current > > configuration, and run through the DPDK crypto device setup process > > and CN10K autotest (not passing currently). I am guessing there is > > some error in our configuration. My coworker Patrick Robb has > > mentioned he met with Hiral previously and it was a big help for > > understanding how to flash the correct firmware, build the SDK and > > tftpboot it, chroot to Ubuntu etc. I hope we can do something similar > > to clear up the confusion regarding crypto devs. What timezones are > > you in? I would be happy to schedule a Zoom call. > > > > Otherwise, I will share some of the system info and the process I have > > run through below, which might begin to give you an idea regarding our > > status: > > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > Marvell CN10k Boot Stub > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > Firmware Version: 2024-12-07 02:04:42 > > EBF Version: 12.24.11, Branch: > > /MarvellSDK/base-SDK12.24.11/cn10ka-release-output/build/marvell-external= -fw-SDK12.24.11/firmware/ebf, > > Built: Sat, 07 Dec 2024 02:02:27 +0000 > > > > Board Model: crb106 > > Board Revision: r1p1 > > Board Serial: > > > > Chip: 0xb9 Pass A1 > > SKU: MV-CN10624-A1-AAP > > LLC: 49152 KB > > Boot: SPI1_CS0,EMMC_CS0, using SPI1_CS0 > > AVS: Enabled > > > > I am setting up 1 crypto virtual function using the commands here: > > https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__doc.dpdk.org_guide= s_cryptodevs_cnxk.html-23initialization&d=3DDwIBaQ&c=3DnKjWec2b6R0mOyPaz7xt= fQ&r=3DvGy6A_Vxl0vuken84vHnqSHz1sugoMRzgsw2uuNRAQ4&m=3DdN2bwgTF6BzuBPsPbKfZ= fmAua-foxlSSnMAoU8EjwCE3XN40flneiz1d7Mwl83iN&s=3D_d4kcuFSGcAGResAexjf_pFNDJ= 0Szm68pM2tw5BFzUM&e=3D > > > > So afterwards I am left with 1 VF bound to vfio-pci at 0002:10.00.1 > > > > At this stage, according to the docs I should be able to launch > > dpdk-test and run the cn10k symmetrical crypto autotest, using the > > commands below: > > > > ``` > > ./dpdk-test > > RTE>>cryptodev_cn10k_autotest > > ``` > > > > However, the auto tests fail and fall into an error loop which I have > > attached the logs of in this email. > > > > Here is the EAL output from the logs: > > > > EAL: Detected CPU lcores: 24 > > EAL: Detected NUMA nodes: 1 > > EAL: Detected static linkage of DPDK > > EAL: Multi-process socket /var/run/dpdk/rte/mp_socket > > EAL: Selected IOVA mode 'VA' > > EAL: VFIO support initialized > > EAL: Using IOMMU type 1 (Type 1) > > CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM) > > CRYPTODEV: Creating cryptodev 0002:20:00.1 > > CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id: > > 0, max queue pairs: 0 > > APP: HPET is not enabled, using TSC as default timer > > > > In the EAL output, max queue pairs is 0 even though in the docs, it > > says the Maximum queue pairs limit is set to a default of 63. Could > > this be related to the issue? > > > > Also, here is my kernel cmdline parameters: > > > > console=3DttyAMA0,115200n8 earlycon=3Dp1011,0x87e028000000 maxcpus=3D24 > > rootwait root=3D/dev/nvme0n1p1 rw coherent_pool=3D16M > > default_hugepagesz=3D512M hugepagesz=3D512M hugepages=3D8 > > > > Does this look correct? > > > > I have also tried setting `iommu.passthrough=3D1` in the boot arguments > > but that resulted in the same dpdk-test failure. > > > > Best Regards, > > Cody Cheng > > --0000000000009cddfb062a0b3442 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Bharath,

Apologies for my delay in r= esponse. That's strange that it is working on your system. Thank you fo= r testing this, and thanks again for meeting the other day.

<= /div>
I do not see any difference in our bootargs which is likely to ca= use this cryptodev issue. If the binary dpdk-test that our native build is = producing is valid (since it worked on your system), and we are using the s= ame hardware (I think we are both on cn10k), then perhaps the software envi= ronment is to blame. Since we just flashed firmware=C2=A0and built the late= st SDK, I don't think that is an issue but we can re-do it if you think= it makes sense.=C2=A0

One thing I can do is re-do= the setup of the SDK kernel=C2=A0+ ubuntu rootfs, on a separate partition,= boot to that environment and attempt to use the dpdk-test binary there. Wh= at I will use for this process is the "Booting to Ubuntu rootfs using = Velox SDK kernel" from=C2=A0doc-base-SDK12.24.11/kernel/ubuntu_rootfs.= html. Someone else on our team did this before, and although I believe he d= id it all according to the docs, it doesn't hurt to run through it agai= n to make sure.

Any other troubleshooting ideas ar= e welcome,=C2=A0if you have any! Also, since Marvell is a member of our lab= , as always I can grant VPN access to anyone if they want to poke around th= is system!=C2=A0 =3DI am on vacation for the next two weeks for winter holi= days, but I will make sure to work on this ASAP when I'm back and repor= t back to you all what happened.=C2=A0

Thanks and = happy holidays.
-Patrick

On Thu, Dec 19, 2024 at 8:35=E2=80= =AFAM Anoob Joseph <anoobj@marvell.com> wrote:

Hi Vivek,

=C2=A0

We do not support these cases. The opcodes are optim= ized for PDCP use case and in the internal branch we have these tests disab= led.

=C2=A0

Thanks,

Anoob

=C2=A0

From: Vivek Garg <vgarg@marvell.com>
Sent: Thursday, December 19, 2024 6:18 PM
To: JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>= ;; Patrick Robb <= probb@iol.unh.edu>; Hiral Shah <hshah@marvell.com>; Anoob Joseph <anoobj@marvell.com>=
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; ci@dpdk.org; Akhil Goyal <= gakhil@marvell.com>; Anoob Joseph <anoobj@marvell.com>; Jerin Jacob <jerinj@marvell.com&g= t;
Subject: RE: [EXTERNAL] CN10K Crypto Test Issue

=C2=A0

HI Anoob,

Below Jira created for snow 3G Test Failures in cryptodev_cn10k_autotest te= sts on 106 with native build binary.

[IPBUSW-58120] SNOW 3G Test Suite are failing in = cryptodev_cn10k_autotest tests on 106 with native build binary. - Marvell J= ira Production System

=C2=A0

Thanks,

Vivek

=C2=A0

=C2=A0

From: JogaRao Nartu <njogarao@marvell.com>
Sent: Thursday, December 19, 2024 5:46 PM
To: Bharath Rajendra <brajendra@marvell.com>; Patrick Robb <probb@iol.unh.edu>; Hira= l Shah <hshah@mar= vell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; ci@dpdk.org; Akhil Goy= al <gakhil@marve= ll.com>; Vivek Garg <vgarg@marvell.com>; Anoob Joseph <anoobj@marvell.com>; Jerin Jacob <je= rinj@marvell.com>
Subject: RE: [EXTERNAL] CN10K Crypto Test Issue

=C2=A0

++

=C2=A0

From: Bharath Rajendra <brajendra@marvell.com>
Sent: Thursday, December 19, 2024 5:44 PM
To: Patrick Robb <probb@iol.unh.edu>; Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; ci@dpdk.org; Akhil Goy= al <gakhil@marve= ll.com>; Vivek Garg <vgarg@marvell.com>
Subject: RE: [EXTERNAL] CN10K Crypto Test Issue

=C2=A0

Hi Patrick,

=C2=A0

We followed the instructions which you used and also= the application which you shared over email.

On our setup it is working as expected. Attached the= complete logs for the reference.

=C2=A0

Bootargs:

console=3DttyAMA0,115200n8 earlycon=3Dpl011,0x87e028= 000000 maxcpus=3D24 rootwait rw root=3D/dev/nfs nfsroot=3D10.29.56.91:/srv/= tftp/regression-debug-2980-db-cn106xx-crb-b0-cisco-267/dut/rootfs,v3,tcp ip= =3Ddhcp coherent_pool=3D16M default_hugepagesz=3D512M hugepagesz=3D512M hugepages=3D8

=C2=A0

Enabling CPT VF=E2=80=99s:

# echo 1 > /sys/bus/pci/devices/0002:20:00.0/srio= v_numvfs

#/usr/bin/dpdk-devbind.py -b vfio-pci 0002:20:00.1

Setting up huge pages:

#mkdir -p /mnt/huge

#mount -t hugetlbfs nodev /mnt/huge

=C2=A0

Note: cryptodev_cn10k_asymautotest works without any= issues. But with cryptodev_cn10k_autotest observed few test failure, this = we will track internally with dev team. But we are not observing =E2=80=9Cr= equest timeout error=E2=80=9D

=C2=A0

Regards

Bharath Rajendra

=C2=A0

From: Patrick Robb <probb@iol.unh.edu>
Sent: Thursday, December 19, 2024 12:29 AM
To: Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>; ci@dpdk.org; Akhil Goy= al <gakhil@marve= ll.com>
Subject: Re: [EXTERNAL] CN10K Crypto Test Issue

=C2=A0

Hi Bharath= and others, Here is the download link to the dpdk-test produced with the n= ative compile on the cn10k host: https:=E2=80=8A//drive.=E2=80=8Agoogle.=E2= =80=8Acom/file/d/127sIjCok3ErxAjrvfncWbv7BOmgL8m6D/view?usp=3Dsharing Thanks, looking forward to hearing back

=

Hi Bharath and others,

=C2=A0

Here is the download link to the dpdk-test produced = with the native compile on the cn10k host:=C2=A0https:= //drive.google.com/file/d/127sIjCok3ErxAjrvfncWbv7BOmgL8m6D/view?usp=3Dshar= ing

=C2=A0

Thanks, looking forward=C2=A0to hearing back from yo= u about how a native build works on your setup. And, apologies for the late= meeting time for you - I did not realize which time zone you were in. If i= t turns out that a followup meeting is required I will be sure to schedule it earlier in the day.

=C2=A0

I'm also adding the DPDK crypto tree maintainer = (Akhil Goyal) to the CC list for this thread.

=C2=A0

Best,

Patrick

=C2=A0

On Wed, Dec 18, 2024 at 12:53=E2=80=AFPM Hiral Shah = <hshah@marvell.co= m> wrote:

=C2=A0

Looks like meeting is over.=C2=A0<= /p>

=C2=A0

Thanks Bharath!

=C2=A0

Regards,<= u>

Hiral<= /u>

From: Patrick Robb <probb@iol.unh.edu>
Sent: Wednesday, December 18, 2024 9:45 AM
To: Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>; ci@dpdk.org <ci@dpdk.org>
Subject: Re: [EXTERNAL] CN10K Crypto Test Issue

=C2=A0

No worries= , Bharath and the others are demonstrating the driver binding and autotest = procedure. On Wed, Dec 18, 2024 at 12:=E2=80=8A37 PM Hiral Shah <hshah@= =E2=80=8Amarvell.=E2=80=8Acom> wrote: Hi Cody, Patrick, Give me 10 -15 more meeting. I am on another call= .=E2=80=8A

No worries, Bharath and the others are demonstrating= the driver binding and autotest procedure.

=C2=A0

On Wed, Dec 18, 2024 at 12:37=E2=80=AFPM Hiral Shah = <hshah@marvell.co= m> wrote:

Hi Cody, Patrick,

=C2=A0

Give me 10 -15 more meeting. I am on another call.=C2= =A0

=C2=A0

=C2=A0

Regards,<= u>

Hiral<= /u>

From: Patrick Robb <probb@iol.unh.edu>
Sent: Monday, December 16, 2024 1:57 PM
To: Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>; ci@dpdk.org <ci@dpdk.org>
Subject: Re: [EXTERNAL] CN10K Crypto Test Issue

=C2=A0

Hi Hiral, = Sorry about the last minute planning today - I am scheduling a call for us = for Wednesday at 9:=E2=80=8A30AM PST. Cody will be in class at that time bu= t I will be available and I believe I know all the details of his issue. ----------= ---------------------------------------------------------------------------= ----------------------

Hi Hiral,

=C2=A0

Sorry about the last minute planning today - I am sc= heduling a call for us for Wednesday at 9:30AM PST. Cody will be in class a= t that time but I will be available and I believe I know all the details of= his issue.=C2=A0

=C2=A0

----------------------------------------------------= -------------------------------------------------------

=C2=A0

Patrick Robb is inviting you to a scheduled Zoom mee= ting.

Topic: Marvell Crypto Sync
Time: Dec 18, 2024 12:30 PM Eastern Time (US and Canada)

Join from PC, Mac, Linux, iOS or Android: https://unh.zoom.us/j/93859170209

Keyboard shortcuts are available to navigate this Zoom meeting or webinar: = https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard-f= or-Zoom
=C2=A0
Or iPhone one-tap: =C2=A013052241968,93859170209# or 13092053325,9385917020= 9#

Or Telephone:
=C2=A0 =C2=A0 Dial: +1 305 224 1968 (US Toll)
=C2=A0 =C2=A0 Meeting ID: 938 5917 0209
=C2=A0 =C2=A0 International numbers available: https://unh.zoom.us/u/acTtiNQKou

Or a H.323/SIP room system:
=C2=A0 =C2=A0 H.323: rc.unh.edu or 144.195.19.161 (US West) or 206.247.11.121 (US East)
=C2=A0 =C2=A0 Meeting ID: 938 5917 0209
=C2=A0 =C2=A0 SIP: 93859170209@zoomcrc.com

TROUBLESHOOTING STEPS:

Audio Echo In A Meeting: https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeting=

Want to Join a Test Meeting?: https://zoom.us/test

=C2=A0

On Mon, Dec 16, 2024 at 3:51=E2=80=AFPM Patrick Robb= <probb@iol.unh.e= du> wrote:

Thanks Hiral for the offer of help, here is a zoom i= nvite for a meeting from 1pm-2pm PST today (in 10 minutes).

=C2=A0

Sorry for the last notice, I can certainly reschedul= e if needed.

=C2=A0

Patrick Robb is inviting you to a scheduled Zoom mee= ting.

Topic: Marvell DPDK Cryptodev sync
Time: Dec 16, 2024 04:00 PM Eastern Time (US and Canada)

Join from PC, Mac, Linux, iOS or Android: https://unh.zoom.us/j/99749831096

Keyboard shortcuts are available to navigate this Zoom meeting or webinar: = https://support.zoom.us/hc/en-us/articles/205683899-Hot-Keys-and-Keyboard-f= or-Zoom
=C2=A0
Or iPhone one-tap: =C2=A016468769923,99749831096# or 16469313860,9974983109= 6#

Or Telephone:
=C2=A0 =C2=A0 Dial: +1 646 876 9923 (US Toll)
=C2=A0 =C2=A0 Meeting ID: 997 4983 1096
=C2=A0 =C2=A0 International numbers available: https://unh.zoom.us/u/aAZFiJCIr

Or a H.323/SIP room system:
=C2=A0 =C2=A0 H.323: rc.unh.edu or 144.195.19.161 (US West) or 206.247.11.121 (US East)
=C2=A0 =C2=A0 Meeting ID: 997 4983 1096
=C2=A0 =C2=A0 SIP: 99749831096@zoomcrc.com

TROUBLESHOOTING STEPS:

Audio Echo In A Meeting: https://support.zoom.us/hc/en-us/articles/202050538-Audio-Echo-In-A-Meeting=

Want to Join a Test Meeting?: https://zoom.us/test

=C2=A0

On Mon, Dec 16, 2024 at 2:39=E2=80=AFPM Patrick Robb= <probb@iol.unh.e= du> wrote:

Thanks, just confirming is this pacific time?=

=C2=A0

On Mon, Dec 16, 2024 at 2:27=E2=80=AFPM Hiral Shah &= lt;hshah@marvell.com= > wrote:

Sure!

=C2=A0

We can have sync up today between 1PM -3 PM or Wednesda= y 8:30AM -1 PM.=C2=A0

=C2=A0

=C2=A0

Regards,<= u>

Hiral<= /u>

From: Patrick Robb <probb@iol.unh.edu>
Sent: Monday, December 16, 2024 10:55 AM
To: Hiral Shah <hshah@marvell.com>
Cc: Cody Cheng <ccheng@iol.unh.edu>; Gnanesh Kambalu Palanethra <gpalanethra@marvell.c= om>; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>; ci@dpdk.org <ci@dpdk.org>
Subject: Re: [EXTERNAL] CN10K Crypto Test Issue

=C2=A0

Hi Hiral, = The cnxk crypto device VF creation and driver binding steps that Cody wrote= in his email are actually straight from the SDK document. Specifically he followed the steps from doc-base-SDK12.=E2=80=8A24.=E2=80=8A11/dpdk/pmd/rt= e_cryptodev.=E2=80=8Ahtml#initialization

Hi Hiral,

=C2=A0

The cnxk=C2=A0crypto device VF creation and driver b= inding steps that Cody wrote in his email are actually straight from the SD= K document. Specifically he followed the steps from=C2=A0doc-base-SDK12.24.= 11/dpdk/pmd/rte_cryptodev.html#initialization

=C2=A0

Thanks for offering a sync up - this would be ideal = as we are still stuck. We can schedule a Zoom and invite you. Do I remember= correctly that you are in the pacific time zone? Is any particular day thi= s week good for you?=C2=A0

=C2=A0

Thanks for all the help.

-Patrick

=C2=A0

On Mon, Dec 16, 2024 at 1:33=E2=80=AFPM Hiral Shah &= lt;hshah@marvell.com= > wrote:

Hi Cody,=C2=A0

=C2=A0

Can you please refer our SDK document? It should have c= lear instructions. We can sync up if you still have any questions.=C2=A0=

=C2=A0

Regards,<= u>

Hiral<= /u>

From: Cody Cheng <ccheng@iol.unh.edu>
Sent: Friday, December 13, 2024 11:47 AM
To: Gnanesh Kambalu Palanethra <gpalanethra@marvell.com>; Hiral Shah <= ;hshah@marvell.com>
Cc: JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>= ;; Patrick Robb <= probb@iol.unh.edu>; ci@dpdk.org <ci@dpdk.org>
Subject: [EXTERNAL] CN10K Crypto Test Issue

=C2=A0

Hi Gnanesh= & Hiral, My name is Cody Cheng, I'm a tester at the University of = New Hampshire DPDK Community Test Lab. We are hosting a CN10K board here wh= ich is currently running some ethernet device tests on DPDK, and we would like to extend= 

Hi Gnanesh & Hiral,
=C2=
=A0
My name is=
 Cody Cheng, I'm a tester at the University of New Hampshire<=
/u>
DPDK Commu=
nity Test Lab. We are hosting a CN10K board here which is
currently =
running some ethernet device tests on DPDK, and we would
like to ex=
tend our testing to include crypto device testing. Gnanesh
has writte=
n a patch which adds testcases to the DPDK Test Suite which
should all=
ow us to do so.
=C2=
=A0
However, I=
 am running into difficulties with the crypto devices I
create in =
DPDK from the CN10K board. I would appreciate it if I can
sync with =
one of you next week so that I can show our current

configurat=
ion, and run through the DPDK crypto device setup process


and CN10K =
autotest (not passing currently). I am guessing there is


some error=
 in our configuration. My coworker Patrick Robb has

mentioned =
he met with Hiral previously and it was a big help for=



understand=
ing how to flash the correct firmware, build the SDK and


tftpboot i=
t, chroot to Ubuntu etc. I hope we can do something similar


to clear u=
p the confusion regarding crypto devs. What timezones are


you in? I =
would be happy to schedule a Zoom call.


=C2=
=A0


Otherwise,=
 I will share some of the system info and the process I have<=
/span>


run throug=
h below, which might begin to give you an idea regarding our<=
/span>


status:=



=C2=
=A0


=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<=
/span>


Marvell CN=
10k Boot Stub


=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<=
/span>


Firmware V=
ersion: 2024-12-07 02:04:42


EBF Versio=
n: 12.24.11, Branch:


/MarvellSD=
K/base-SDK12.24.11/cn10ka-release-output/build/marvell-external-fw-SDK12.24=
.11/firmware/ebf,


Built: Sat=
, 07 Dec 2024 02:02:27 +0000


=C2=
=A0


Board Mode=
l:=C2=A0=C2=A0=C2=A0 crb106


Board Revi=
sion: r1p1


Board Seri=
al:=C2=A0=C2=A0 <redacted>


=C2=
=A0


Chip:=C2=
=A0 0xb9 Pass A1


SKU:=C2=A0=
=C2=A0 MV-CN10624-A1-AAP


LLC:=C2=A0=
=C2=A0 49152 KB


Boot:=C2=
=A0 SPI1_CS0,EMMC_CS0, using SPI1_CS0


AVS:=C2=A0=
=C2=A0 Enabled


=C2=
=A0


I am setti=
ng up 1 crypto virtual function using the commands here:


https://ur=
ldefense.proofpoint.com/v2/url?u=3Dhttps-3A__doc.dpdk.org_guides_cryptodevs=
_cnxk.html-23initialization&d=3DDwIBaQ&c=3DnKjWec2b6R0mOyPaz7xtfQ&a=
mp;r=3DvGy6A_Vxl0vuken84vHnqSHz1sugoMRzgsw2uuNRAQ4&m=3DdN2bwgTF6BzuBPsP=
bKfZfmAua-foxlSSnMAoU8EjwCE3XN40flneiz1d7Mwl83iN&s=3D_d4kcuFSGcAGResAex=
jf_pFNDJ0Szm68pM2tw5BFzUM&e=3D


=C2=
=A0


So afterwa=
rds I am left with 1 VF bound to vfio-pci at 0002:10.00.1


=C2=
=A0


At this st=
age, according to the docs I should be able to launch<=
/pre>

dpdk-test =
and run the cn10k symmetrical crypto autotest, using the


commands b=
elow:


=C2=
=A0


```=



./dpdk-tes=
t


RTE>>=
;cryptodev_cn10k_autotest


```=



=C2=
=A0


However, t=
he auto tests fail and fall into an error loop which I have


attached t=
he logs of in this email.


=C2=
=A0


Here is th=
e EAL output from the logs:


=C2=
=A0


EAL: Detec=
ted CPU lcores: 24


EAL: Detec=
ted NUMA nodes: 1


EAL: Detec=
ted static linkage of DPDK


EAL: Multi=
-process socket /var/run/dpdk/rte/mp_socket


EAL: Selec=
ted IOVA mode 'VA'


EAL: VFIO =
support initialized


EAL: Using=
 IOMMU type 1 (Type 1)


CNXK: RoC =
Model: cn10ka_a1 (HW_PLATFORM)


CRYPTODEV:=
 Creating cryptodev 0002:20:00.1


CRYPTODEV:=
 Initialisation parameters - name: 0002:20:00.1,socket id:


0, max que=
ue pairs: 0


APP: HPET =
is not enabled, using TSC as default timer


=C2=
=A0


In the EAL=
 output, max queue pairs is 0 even though in the docs, it


says the M=
aximum queue pairs limit is set to a default of 63. Could


this be re=
lated to the issue?


=C2=
=A0


Also, here=
 is my kernel cmdline parameters:


=C2=
=A0


console=3D=
ttyAMA0,115200n8 earlycon=3Dp1011,0x87e028000000 maxcpus=3D24=



rootwait r=
oot=3D/dev/nvme0n1p1 rw coherent_pool=3D16M


default_hu=
gepagesz=3D512M hugepagesz=3D512M hugepages=3D8


=C2=
=A0


Does this =
look correct?


=C2=
=A0


I have als=
o tried setting `iommu.passthrough=3D1` in the boot arguments=



but that r=
esulted in the same dpdk-test failure.


=C2=
=A0


Best Regar=
ds,


Cody Cheng=
--0000000000009cddfb062a0b3442--