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Tue, 2 Feb 2021 14:13:44 +0000 From: Tal Shnaiderman To: Bruce Richardson , Leyi Rong CC: "david.marchand@redhat.com" , "qi.z.zhang@intel.com" , "ferruh.yigit@intel.com" , NBU-Contact-Thomas Monjalon , "pallavi.kadam@intel.com" , "ranjit.menon@intel.com" , "beilei.xing@intel.com" , "aconole@redhat.com" , "dev@dpdk.org" , "ci@dpdk.org" Thread-Topic: [PATCH] net/i40e: disable AVX512 with MinGW Thread-Index: AQHW+UWrrcZ43S+4YEGun/j31Ja6dapEqLsAgAA/T3A= Date: Tue, 2 Feb 2021 14:13:44 +0000 Message-ID: References: <20210202090639.83164-1-leyi.rong@intel.com> <20210202102450.GA139@bricha3-MOBL.ger.corp.intel.com> In-Reply-To: <20210202102450.GA139@bricha3-MOBL.ger.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=nvidia.com; x-originating-ip: [77.137.141.17] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2c1ca900-fb8d-4c75-44b1-08d8c784c02e x-ms-traffictypediagnostic: DM6PR12MB3497: x-ld-processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr x-microsoft-antispam-prvs: x-header: ProcessedBy-CMR-outbound x-ms-oob-tlc-oobclassifiers: OLM:8882; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3945.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2c1ca900-fb8d-4c75-44b1-08d8c784c02e X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Feb 2021 14:13:44.6413 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pflJ784auYhFTq6NVhsHGJLxa1i6vAsC1DK7+SlJFU6UrcHsXfuBTR31wBm0l5e5je9wUBYJx+FyI9+g7fEcBg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3497 X-OriginatorOrg: Nvidia.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1612275230; bh=/4p0GK9ePiHxI03F8uhU6JpZwjFlX1Vxn5T9tZB6olY=; h=X-PGP-Universal:ARC-Seal:ARC-Message-Signature: ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic: Thread-Index:Date:Message-ID:References:In-Reply-To: Accept-Language:Content-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-ms-office365-filtering-correlation-id: x-ms-traffictypediagnostic:x-ld-processed: x-microsoft-antispam-prvs:x-header:x-ms-oob-tlc-oobclassifiers: x-ms-exchange-senderadcheck:x-microsoft-antispam: x-microsoft-antispam-message-info:x-forefront-antispam-report: x-ms-exchange-antispam-messagedata:x-ms-exchange-transport-forked: Content-Type:Content-Transfer-Encoding:MIME-Version: X-MS-Exchange-CrossTenant-AuthAs: X-MS-Exchange-CrossTenant-AuthSource: X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-CrossTenant-userprincipalname: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg; b=CuVvXF6CGyalpi++0s4Lb/d9a+cX4prhNO2SLg1XcExuW8ZO0qVB1p5idotvChL85 bwjcxS7VxAM0lOwpHt1GN7O4G5bMspE6ZAlAEnp0bwkZanadBiZiGQi9oKniZl0xE0 rvOprMGEnShzjboemwBIWCMjk8jLrI7gPl0f8LlRaVeNx8Gc6K5aq4nh6yzTwZ7Ze7 ClX59m0AZHVn29AubsqA8OotNqR/Ar5NkhI5jWvNtdRc7QJwzUtGVK13f0zTBm602b 8M/qei9fI4yNZHxm7TR7x/ODIrzHoB5QhbV+mS3HKHFxuIrdeuwajHURDcH2x6iDpW Ukro+BMtOLqUw== Subject: Re: [dpdk-ci] [PATCH] net/i40e: disable AVX512 with MinGW X-BeenThere: ci@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK CI discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: ci-bounces@dpdk.org Sender: "ci" > Subject: Re: [PATCH] net/i40e: disable AVX512 with MinGW >=20 > External email: Use caution opening links or attachments >=20 >=20 > On Tue, Feb 02, 2021 at 05:06:39PM +0800, Leyi Rong wrote: > > Disable i40e AVX512 code path for Windows build regardless of CPU > > capability to avoid the MinGW build error: > > Error: invalid register for .seh_savexmm > > > > Signed-off-by: Leyi Rong > > --- > > drivers/net/i40e/meson.build | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/net/i40e/meson.build > > b/drivers/net/i40e/meson.build index f5fc5a17e..26cd201ee 100644 > > --- a/drivers/net/i40e/meson.build > > +++ b/drivers/net/i40e/meson.build > > @@ -56,6 +56,7 @@ if arch_subdir =3D=3D 'x86' > > > > if is_windows and cc.get_id() !=3D 'clang' > > i40e_avx512_cc_support =3D false > > + i40e_avx512_cpu_support =3D false > > endif > > >=20 > This fix seems to imply that there is something else wrong in the logic i= n the > build file. If the compiler does not support avx512, the fact that the CP= U > supports it should be completely irrelevant. Therefore, I think a more co= rrect > fix (logically) should be to remove the "i40e_avx512_cpu_support" > from the next "if" condition, and only check the compiler support. We don= 't > do anything with the cpu support variable. Moreover, this patch doesn't resolve the issue [1]. [1] http://mails.dpdk.org/archives/test-report/2021-February/177665.html >=20 > /Bruce