From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by dpdk.org (Postfix) with ESMTP id 349DB9E3 for ; Wed, 28 Feb 2018 10:56:21 +0100 (CET) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w1S9smTS061777 for ; Wed, 28 Feb 2018 04:56:20 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0a-001b2d01.pphosted.com with ESMTP id 2gdrxtue2u-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 28 Feb 2018 04:56:20 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 28 Feb 2018 09:56:18 -0000 Received: from b06cxnps4075.portsmouth.uk.ibm.com (9.149.109.197) by e06smtp14.uk.ibm.com (192.168.101.144) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Wed, 28 Feb 2018 09:56:15 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w1S9uFNq54394902; Wed, 28 Feb 2018 09:56:15 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 94E7511C052; Wed, 28 Feb 2018 09:49:08 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 045FB11C04C; Wed, 28 Feb 2018 09:49:07 +0000 (GMT) Received: from ADMINIB2M8Q79C (unknown [9.186.58.139]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 28 Feb 2018 09:49:06 +0000 (GMT) From: "Chao Zhu" To: "'Gowrishankar'" , Cc: , References: In-Reply-To: Date: Wed, 28 Feb 2018 17:56:13 +0800 MIME-Version: 1.0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 15.0 Thread-Index: AQFwZhrdDPX7ikNob3Yh5jujyvW9UKSAKH4A Content-Language: zh-cn X-TM-AS-GCONF: 00 x-cbid: 18022809-0016-0000-0000-0000052ABBA5 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18022809-0017-0000-0000-00002866EC84 Message-Id: <000001d3b07a$5f911a40$1eb34ec0$@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-28_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802280120 Subject: Re: [dpdk-dev] [PATCH] eal/ppc: fix rte_smp_mb for a compilation error with else clause X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Feb 2018 09:56:21 -0000 > -----Original Message----- > From: Gowrishankar [mailto:gowrishankar.m@linux.vnet.ibm.com] > Sent: 2018=C4=EA2=D4=C227=C8=D5 23:14 > To: dev@dpdk.org > Cc: Chao Zhu ; stable@dpdk.org; > thomas@monjalon.net; Gowrishankar Muthukrishnan > > Subject: [PATCH] eal/ppc: fix rte_smp_mb for a compilation error with = else > clause >=20 > From: Gowrishankar Muthukrishnan >=20 > This patch fixes the compilation problem with rte_smp_mb, when there = is else > clause following it, as in test_barrier.c. >=20 > Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power") > Cc: stable@dpdk.org >=20 > Signed-off-by: Gowrishankar Muthukrishnan > > --- > lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > index 39fce7b..1821774 100644 > --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > @@ -55,7 +55,7 @@ > * Guarantees that the LOAD and STORE operations generated before the > * barrier occur before the LOAD and STORE operations generated = after. > */ > -#define rte_mb() {asm volatile("sync" : : : "memory"); } > +#define rte_mb() asm volatile("sync" : : : "memory") >=20 > /** > * Write memory barrier. > -- > 1.9.1 Acked-by: Chao Zhu