From: Tony Lu <zlu@ezchip.com>
To: 'Bruce Richardson' <bruce.richardson@intel.com>
Cc: dev@dpdk.org
Subject: Re: [dpdk-dev] [PATCH v3 08/12] mempool: allow config override on element alignment
Date: Tue, 7 Jul 2015 17:15:41 +0800 [thread overview]
Message-ID: <000f01d0b895$8ccbf8c0$a663ea40$@com> (raw)
In-Reply-To: <20150706153758.GD3680@bricha3-MOBL3>
>-----Original Message-----
>From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Bruce Richardson
>Sent: Monday, July 06, 2015 11:38 PM
>To: Zhigang Lu
>Cc: dev@dpdk.org
>Subject: Re: [dpdk-dev] [PATCH v3 08/12] mempool: allow config override on
>element alignment
>
>On Mon, Jul 06, 2015 at 04:51:33PM +0800, Zhigang Lu wrote:
>> On TILE-Gx and TILE-Mx platforms, the buffers fed into the hardware
>> buffer manager require a 128-byte alignment. With this change, we
>> allow configuration based override of the element alignment, and
>> default to RTE_CACHE_LINE_SIZE if left unspecified.
>>
>> Change-Id: I9cd789d92b0bc9c8f44a633de59bb04d45d927a7
>> Signed-off-by: Zhigang Lu <zlu@ezchip.com>
>
>This looks an OK change. However, would it be worthwhile making this a
runtime
>parameter rather than a compile-time one? Is it likely that we will ever
have a
>case where someone wants two mempools with different alignments (and
>where using the larger of the two would be problematic)?
For now, I don't think it is very much worthwhile making this a runtime
parameter,
since doing so requires changing the mempool library API, and also the users
of mempool
do not quite care about the underlying alignments. Currently, the alignment
for mempool
objects is mostly a hardware requirement (currently RTE_CACHE_LINE_SIZE for
good
performance). And now we are defining a new RTE_MEMPOOL_ALIGN for mempool
alignment requirement for cases where someone needs other alignments than
RTE_CACHE_LINE_SIZE.
If someone wants two mempools with different alignments, using the larger
one would
not be a problem in current mempool implementation. Because even for the
case where
there is one alignment requirement RTE_CACHE_LINE_SIZE, we would provide
larger one
(2* RTE_CACHE_LINE_SIZE and larger) for allocated mempool objects, as those
objects
are continuous in memory. So we could not avoid larger one in current
implementation.
Thanks again for reviewing!
-Zhigang
>/Bruce
next prev parent reply other threads:[~2015-07-07 9:16 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-06 8:51 [dpdk-dev] [PATCH v3 00/12] Introducing the TILE-Gx platform Zhigang Lu
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 01/12] test: limit x86 cpuflags checks to x86 builds Zhigang Lu
2015-07-06 10:53 ` Bruce Richardson
2015-07-07 8:21 ` Tony Lu
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 02/12] hash: fix compilation on non-X86 platforms Zhigang Lu
2015-07-06 11:15 ` Bruce Richardson
2015-07-07 8:24 ` Tony Lu
2015-07-07 14:52 ` Sanford, Robert
2015-07-08 8:21 ` Tony Lu
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 03/12] hash: check SSE flags only on x86 builds Zhigang Lu
2015-07-06 15:32 ` Bruce Richardson
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 04/12] eal: allow empty compile time flags Zhigang Lu
2015-07-06 15:33 ` Bruce Richardson
2015-07-09 0:46 ` Thomas Monjalon
2015-07-09 4:20 ` Tony Lu
2015-07-09 6:49 ` damu
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 05/12] config: remove RTE_LIBNAME definition Zhigang Lu
2015-07-06 15:34 ` Bruce Richardson
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 06/12] memzone: refactor rte_memzone_reserve() variants Zhigang Lu
2015-07-09 0:51 ` Thomas Monjalon
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 07/12] memzone: allow multiple pagesizes to be requested Zhigang Lu
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 08/12] mempool: allow config override on element alignment Zhigang Lu
2015-07-06 15:37 ` Bruce Richardson
2015-07-07 9:15 ` Tony Lu [this message]
2015-07-07 10:10 ` Bruce Richardson
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 09/12] tile: add page sizes for TILE-Gx/Mx platforms Zhigang Lu
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 10/12] tile: initial TILE-Gx support Zhigang Lu
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 11/12] tile: Add TILE-Gx mPIPE poll mode driver Zhigang Lu
2015-07-06 8:51 ` [dpdk-dev] [PATCH v3 12/12] maintainers: claim responsibility for TILE-Gx platform Zhigang Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='000f01d0b895$8ccbf8c0$a663ea40$@com' \
--to=zlu@ezchip.com \
--cc=bruce.richardson@intel.com \
--cc=dev@dpdk.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).