From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by dpdk.org (Postfix) with ESMTP id 257021DBD for ; Tue, 19 Mar 2019 04:24:14 +0100 (CET) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2J3Nws5117001 for ; Mon, 18 Mar 2019 23:24:14 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2rarbjg6un-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 18 Mar 2019 23:24:13 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 19 Mar 2019 03:24:09 -0000 Received: from b06cxnps3075.portsmouth.uk.ibm.com (9.149.109.195) by e06smtp02.uk.ibm.com (192.168.101.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 19 Mar 2019 03:24:06 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2J3O79s45940900 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Mar 2019 03:24:07 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B2832AE04D; Tue, 19 Mar 2019 03:24:07 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 52C4DAE05D; Tue, 19 Mar 2019 03:24:05 +0000 (GMT) Received: from DESKTOP7JL9IS1 (unknown [9.181.88.48]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 19 Mar 2019 03:24:05 +0000 (GMT) From: "Chao Zhu" To: "'Dekel Peled'" Cc: , , , , , References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> In-Reply-To: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> Date: Tue, 19 Mar 2019 11:24:06 +0800 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQI4r1EkqThUtU/R0v+mdcYm+DaxlaVKpnLg Content-Language: zh-cn X-TM-AS-GCONF: 00 x-cbid: 19031903-0008-0000-0000-000002CEF05B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031903-0009-0000-0000-0000223B013E Message-Id: <001d01d4de03$378f18a0$a6ad49e0$@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-19_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903190024 Subject: Re: [dpdk-dev] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Mar 2019 03:24:15 -0000 Dekel£¬ To control the memory order for device memory, I think you should use rte_io_mb() instead of rte_mb(). This will generate correct result. rte_wmb() is used for system memory. > -----Original Message----- > From: Dekel Peled > Sent: Monday, March 18, 2019 8:58 PM > To: chaozhu@linux.vnet.ibm.com > Cc: yskoh@mellanox.com; shahafs@mellanox.com; dev@dpdk.org; > orika@mellanox.com; thomas@monjalon.net; dekelp@mellanox.com; > stable@dpdk.org > Subject: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER > > From previous patch description: "to improve performance on PPC64, use light > weight sync instruction instead of sync instruction." > > Excerpt from IBM doc [1], section "Memory barrier instructions": > "The second form of the sync instruction is light-weight sync, or lwsync. > This form is used to control ordering for storage accesses to system memory > only. It does not create a memory barrier for accesses to device memory." > > This patch removes the use of lwsync, so calls to rte_wmb() and > rte_rmb() will provide correct memory barrier to ensure order of accesses to > system memory and device memory. > > [1] https://www.ibm.com/developerworks/systems/articles/powerpc.html > > Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER") > Cc: stable@dpdk.org > > Signed-off-by: Dekel Peled > --- > lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 8 -------- > 1 file changed, 8 deletions(-) > > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > index ce38350..797381c 100644 > --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > @@ -63,11 +63,7 @@ > * Guarantees that the STORE operations generated before the barrier > * occur before the STORE operations generated after. > */ > -#ifdef RTE_ARCH_64 > -#define rte_wmb() asm volatile("lwsync" : : : "memory") > -#else > #define rte_wmb() asm volatile("sync" : : : "memory") > -#endif > > /** > * Read memory barrier. > @@ -75,11 +71,7 @@ > * Guarantees that the LOAD operations generated before the barrier > * occur before the LOAD operations generated after. > */ > -#ifdef RTE_ARCH_64 > -#define rte_rmb() asm volatile("lwsync" : : : "memory") > -#else > #define rte_rmb() asm volatile("sync" : : : "memory") > -#endif > > #define rte_smp_mb() rte_mb() > > -- > 1.8.3.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 5C744A05FE for ; Tue, 19 Mar 2019 04:24:17 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 828142956; Tue, 19 Mar 2019 04:24:16 +0100 (CET) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by dpdk.org (Postfix) with ESMTP id 257021DBD for ; Tue, 19 Mar 2019 04:24:14 +0100 (CET) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2J3Nws5117001 for ; Mon, 18 Mar 2019 23:24:14 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2rarbjg6un-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 18 Mar 2019 23:24:13 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 19 Mar 2019 03:24:09 -0000 Received: from b06cxnps3075.portsmouth.uk.ibm.com (9.149.109.195) by e06smtp02.uk.ibm.com (192.168.101.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 19 Mar 2019 03:24:06 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2J3O79s45940900 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Mar 2019 03:24:07 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B2832AE04D; Tue, 19 Mar 2019 03:24:07 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 52C4DAE05D; Tue, 19 Mar 2019 03:24:05 +0000 (GMT) Received: from DESKTOP7JL9IS1 (unknown [9.181.88.48]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 19 Mar 2019 03:24:05 +0000 (GMT) From: "Chao Zhu" To: "'Dekel Peled'" Cc: , , , , , References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> In-Reply-To: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> Date: Tue, 19 Mar 2019 11:24:06 +0800 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQI4r1EkqThUtU/R0v+mdcYm+DaxlaVKpnLg Content-Language: zh-cn X-TM-AS-GCONF: 00 x-cbid: 19031903-0008-0000-0000-000002CEF05B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031903-0009-0000-0000-0000223B013E Message-Id: <001d01d4de03$378f18a0$a6ad49e0$@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-19_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903190024 Subject: Re: [dpdk-dev] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Content-Type: text/plain; charset="UTF-8" Message-ID: <20190319032406.S8XGp6rZBk_IThFhfA0xXmq4Up9oCn7HXejL8B1TDLQ@z> Dekel£¬ To control the memory order for device memory, I think you should use rte_io_mb() instead of rte_mb(). This will generate correct result. rte_wmb() is used for system memory. > -----Original Message----- > From: Dekel Peled > Sent: Monday, March 18, 2019 8:58 PM > To: chaozhu@linux.vnet.ibm.com > Cc: yskoh@mellanox.com; shahafs@mellanox.com; dev@dpdk.org; > orika@mellanox.com; thomas@monjalon.net; dekelp@mellanox.com; > stable@dpdk.org > Subject: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER > > From previous patch description: "to improve performance on PPC64, use light > weight sync instruction instead of sync instruction." > > Excerpt from IBM doc [1], section "Memory barrier instructions": > "The second form of the sync instruction is light-weight sync, or lwsync. > This form is used to control ordering for storage accesses to system memory > only. It does not create a memory barrier for accesses to device memory." > > This patch removes the use of lwsync, so calls to rte_wmb() and > rte_rmb() will provide correct memory barrier to ensure order of accesses to > system memory and device memory. > > [1] https://www.ibm.com/developerworks/systems/articles/powerpc.html > > Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER") > Cc: stable@dpdk.org > > Signed-off-by: Dekel Peled > --- > lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 8 -------- > 1 file changed, 8 deletions(-) > > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > index ce38350..797381c 100644 > --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > @@ -63,11 +63,7 @@ > * Guarantees that the STORE operations generated before the barrier > * occur before the STORE operations generated after. > */ > -#ifdef RTE_ARCH_64 > -#define rte_wmb() asm volatile("lwsync" : : : "memory") > -#else > #define rte_wmb() asm volatile("sync" : : : "memory") > -#endif > > /** > * Read memory barrier. > @@ -75,11 +71,7 @@ > * Guarantees that the LOAD operations generated before the barrier > * occur before the LOAD operations generated after. > */ > -#ifdef RTE_ARCH_64 > -#define rte_rmb() asm volatile("lwsync" : : : "memory") > -#else > #define rte_rmb() asm volatile("sync" : : : "memory") > -#endif > > #define rte_smp_mb() rte_mb() > > -- > 1.8.3.1