From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E318BA04BC; Thu, 8 Oct 2020 11:51:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3A6BE1BC29; Thu, 8 Oct 2020 11:51:13 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id D89961E34 for ; Thu, 8 Oct 2020 11:51:10 +0200 (CEST) IronPort-SDR: JK/+ShyBxtcQqo++XAqnDkJF203/JVTWj3F3CxUSPjhcm9yzFSsFabouzWMTW2KaZkQoQiocpN BE+IvG0961AQ== X-IronPort-AV: E=McAfee;i="6000,8403,9767"; a="229496485" X-IronPort-AV: E=Sophos;i="5.77,350,1596524400"; d="scan'208";a="229496485" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2020 02:51:08 -0700 IronPort-SDR: cmCADGMVIoe9aV3fWS4nzQuCGcl5o2rwiWk4WZJ5JNBLJvRyXfvDV1HbRAJ8D/Ho4N97NteQCh sX6WJfmwVBTQ== X-IronPort-AV: E=Sophos;i="5.77,350,1596524400"; d="scan'208";a="461761447" Received: from rnicolau-mobl1.ger.corp.intel.com (HELO [10.251.82.129]) ([10.251.82.129]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2020 02:51:05 -0700 To: David Marchand Cc: dev , Beilei Xing , Jeff Guo , Bruce Richardson , "Ananyev, Konstantin" , Jerin Jacob , "Trahe, Fiona" , Wei Zhao , "Ruifeng Wang (Arm Technology China)" , Qiming Yang , Qi Zhang , "Yigit, Ferruh" , Akhil Goyal , David Christensen References: <1591870283-7776-1-git-send-email-radu.nicolau@intel.com> <20200923142253.18853-1-radu.nicolau@intel.com> From: "Nicolau, Radu" Message-ID: <0328e1eb-e14b-4d67-6e90-36c6fad0c1ec@intel.com> Date: Thu, 8 Oct 2020 10:51:02 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-GB Subject: Re: [dpdk-dev] [PATCH v12 0/5] eal: add WC store functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 10/8/2020 8:28 AM, David Marchand wrote: > On Wed, Sep 23, 2020 at 4:23 PM Radu Nicolau wrote: >> Implement 2 new functions that will enable write combining >> stores depending on architecture. The functions are provided >> as a generic stub and a x86 specific implementation. >> >> The reason to implement these functions is to improve performance >> by reducing the overhead associated with regular mmio writes when >> updating the hardware queue tails and doorbells. > For the record, on which CPU/platform was this tested and how much of > an improvement did you get with this? The improvement varies a lot with the particular usecase and the PMD, so it's difficult to state a number, but there were cases with performance improvements going well into the double digits, with very small bursts applications seeing the most benefits. Tests were done on a Snow Ridge platform. > > I did not see review/ack tokens from other arch maintainers, but since > it has been on the ml for a while, I guess I can proceed as is. > > >> With this patch set the I40E, ICE, IXGBE and QAT PMDs are updated to >> use the write combining store functions with other PMDs to follow. > This series will go through the main repo: copying Ferruh and Akhil for info. > >