From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id C1F3B1CC06 for ; Thu, 5 Apr 2018 16:20:38 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Apr 2018 07:20:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,411,1517904000"; d="scan'208";a="188908706" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga004.jf.intel.com with ESMTP; 05 Apr 2018 07:20:37 -0700 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 5 Apr 2018 07:20:36 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 5 Apr 2018 07:20:36 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.241]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.88]) with mapi id 14.03.0319.002; Thu, 5 Apr 2018 22:20:34 +0800 From: "Zhang, Qi Z" To: Adrien Mazarguil , Thomas Monjalon , "Yigit, Ferruh" , "dev@dpdk.org" CC: "Lu, Wenzhuo" , "Wu, Jingjing" , Ajit Khaparde , "Somnath Kotur" , John Daley , "Hyong Youb Kim" , "Xing, Beilei" , "Ananyev, Konstantin" , Nelio Laranjeiro , Yongseok Koh , Jacek Siuda , Tomasz Duszynski , Dmitri Epshtein , Natalie Samsonov , Jianbo Liu , Andrew Rybchenko , "Pascal Mazon" Thread-Topic: [PATCH v1 11/16] ethdev: refine TPID handling in flow API Thread-Index: AQHTzC2oRN3WVY5R1UaFN1W2wZgCR6PyM9Dg Date: Thu, 5 Apr 2018 14:20:34 +0000 Message-ID: <039ED4275CED7440929022BC67E7061153182FE4@SHSMSX103.ccr.corp.intel.com> References: <20180404150312.12304-1-adrien.mazarguil@6wind.com> <20180404150312.12304-12-adrien.mazarguil@6wind.com> In-Reply-To: <20180404150312.12304-12-adrien.mazarguil@6wind.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1 11/16] ethdev: refine TPID handling in flow API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Apr 2018 14:20:39 -0000 Hi Adrien: > Hi PMD maintainers, while I'm pretty confident in these changes, I could = not > validate them with all devices. >=20 > It would be great if you could apply this patch, run testpmd, create VLAN= flow > rules with/without inner EtherType as described and send matching traffic > while making sure nothing was broken in the process. >=20 > Thanks! > --- > diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c = index > 1b336df74..c6dd889ad 100644 > --- a/drivers/net/i40e/i40e_flow.c > +++ b/drivers/net/i40e/i40e_flow.c > @@ -2490,24 +2490,36 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev > *dev, > "Invalid MAC_addr mask."); > return -rte_errno; > } > + } > + if (eth_spec && eth_mask && eth_mask->type) { > + enum rte_flow_item_type next =3D (item + 1)->type; >=20 > - if ((eth_mask->type & UINT16_MAX) =3D=3D > - UINT16_MAX) { > - input_set |=3D I40E_INSET_LAST_ETHER_TYPE; > - filter->input.flow.l2_flow.ether_type =3D > - eth_spec->type; > + if (eth_mask->type !=3D RTE_BE16(0xffff)) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > + item, > + "Invalid type mask."); > + return -rte_errno; > } >=20 > ether_type =3D rte_be_to_cpu_16(eth_spec->type); > - if (ether_type =3D=3D ETHER_TYPE_IPv4 || > - ether_type =3D=3D ETHER_TYPE_IPv6 || > - ether_type =3D=3D ETHER_TYPE_ARP || > - ether_type =3D=3D outer_tpid) { > + > + if ((next =3D=3D RTE_FLOW_ITEM_TYPE_VLAN && > + ether_type !=3D outer_tpid) || > + (next !=3D RTE_FLOW_ITEM_TYPE_VLAN && > + (ether_type =3D=3D ETHER_TYPE_IPv4 || > + ether_type =3D=3D ETHER_TYPE_IPv6 || > + ether_type =3D=3D ETHER_TYPE_ARP || > + ether_type =3D=3D outer_tpid))) { > rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > "Unsupported ether_type."); > return -rte_errno; > + } else if (next !=3D RTE_FLOW_ITEM_TYPE_VLAN) { > + input_set |=3D I40E_INSET_LAST_ETHER_TYPE; > + filter->input.flow.l2_flow.ether_type =3D > + eth_spec->type; > } > } >=20 > @@ -2518,6 +2530,14 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev > *dev, > case RTE_FLOW_ITEM_TYPE_VLAN: > vlan_spec =3D item->spec; > vlan_mask =3D item->mask; > + > + if (input_set & I40E_INSET_LAST_ETHER_TYPE) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > + item, > + "Unsupported outer TPID."); > + return -rte_errno; > + } Please correct me I'm wrong, now I40E_INSET_LAST_ETHER_TYPE will only be se= t when next !=3D RTE_FLOW_ITEM_TYPE_VLAN while, RTE_FLOW_ITEM_TYPE_VLAN will only be the next to RTE_FLOW_ITEM_TYPE_= ETH for fdir, so above check seems unnecessary ? Thanks Qi > if (vlan_spec && vlan_mask) { > if (vlan_mask->tci =3D=3D > rte_cpu_to_be_16(I40E_TCI_MASK)) { @@ -2526,6 > +2546,33 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev, > vlan_spec->tci; > } > } > + if (vlan_spec && vlan_mask && vlan_mask->inner_type) { > + if (vlan_mask->inner_type !=3D RTE_BE16(0xffff)) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > + item, > + "Invalid inner_type" > + " mask."); > + return -rte_errno; > + } > + > + ether_type =3D > + rte_be_to_cpu_16(vlan_spec->inner_type); > + > + if (ether_type =3D=3D ETHER_TYPE_IPv4 || > + ether_type =3D=3D ETHER_TYPE_IPv6 || > + ether_type =3D=3D ETHER_TYPE_ARP || > + ether_type =3D=3D outer_tpid) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > + item, > + "Unsupported inner_type."); > + return -rte_errno; > + } > + input_set |=3D I40E_INSET_LAST_ETHER_TYPE; > + filter->input.flow.l2_flow.ether_type =3D > + vlan_spec->inner_type; > + } >=20 > pctype =3D I40E_FILTER_PCTYPE_L2_PAYLOAD; > layer_idx =3D I40E_FLXPLD_L2_IDX; > @@ -3284,7 +3331,8 @@ i40e_flow_parse_vxlan_pattern(__rte_unused struct > rte_eth_dev *dev, > case RTE_FLOW_ITEM_TYPE_VLAN: > vlan_spec =3D item->spec; > vlan_mask =3D item->mask; > - if (!(vlan_spec && vlan_mask)) { > + if (!(vlan_spec && vlan_mask) || > + vlan_mask->inner_type) { > rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > @@ -3514,7 +3562,8 @@ i40e_flow_parse_nvgre_pattern(__rte_unused > struct rte_eth_dev *dev, > case RTE_FLOW_ITEM_TYPE_VLAN: > vlan_spec =3D item->spec; > vlan_mask =3D item->mask; > - if (!(vlan_spec && vlan_mask)) { > + if (!(vlan_spec && vlan_mask) || > + vlan_mask->inner_type) { > rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > @@ -4022,7 +4071,8 @@ i40e_flow_parse_qinq_pattern(__rte_unused struct > rte_eth_dev *dev, > vlan_spec =3D item->spec; > vlan_mask =3D item->mask; >=20 > - if (!(vlan_spec && vlan_mask)) { > + if (!(vlan_spec && vlan_mask) || > + vlan_mask->inner_type) { > rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, > item,