From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 85AD21B1B6 for ; Fri, 11 May 2018 14:11:49 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 May 2018 05:11:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,388,1520924400"; d="scan'208";a="54329981" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga001.fm.intel.com with ESMTP; 11 May 2018 05:11:47 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 11 May 2018 05:11:47 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.210]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.179]) with mapi id 14.03.0319.002; Fri, 11 May 2018 20:11:44 +0800 From: "Zhang, Qi Z" To: "Xu, Rosen" , "dev@dpdk.org" , "thomas@monjalon.net" CC: "Xu, Rosen" , "Zhang, Roy Fan" , "Doherty, Declan" , "Richardson, Bruce" , "shreyansh.jain@nxp.com" , "Yigit, Ferruh" , "Ananyev, Konstantin" , "Zhang, Tianfei" , "Liu, Song" , "Wu, Hao" , "gaetan.rivet@6wind.com" Thread-Topic: [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS Thread-Index: AQHT6QKABw0lT9KsFkW79haUKImYpKQqb70g Date: Fri, 11 May 2018 12:11:44 +0000 Message-ID: <039ED4275CED7440929022BC67E70611531B14C3@SHSMSX103.ccr.corp.intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1526027491-30152-1-git-send-email-rosen.xu@intel.com> In-Reply-To: <1526027491-30152-1-git-send-email-rosen.xu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNzlkNjFkZWMtYWQwMi00ODNlLTg1ZTUtZDI0OTYwYTU1MDY4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJ6SkpJNUhjVExVMEVJZlB2SjkxUllDQU43T2hodTQ1SkJscWF2dW80RlVHXC8xTDQrOE5Mc2VMWUtKdmQwb0tTZCJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 May 2018 12:11:50 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Xu, Rosen > Sent: Friday, May 11, 2018 4:31 PM > To: dev@dpdk.org; thomas@monjalon.net > Cc: Xu, Rosen ; Zhang, Roy Fan > ; Doherty, Declan ; > Richardson, Bruce ; shreyansh.jain@nxp.com; > Yigit, Ferruh ; Ananyev, Konstantin > ; Zhang, Tianfei ; > Liu, Song ; Wu, Hao ; > gaetan.rivet@6wind.com > Subject: [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS >=20 > From: "Xu, Rosen" >=20 > Intel FPGA BUS in DPDK > ------------------------- >=20 > This patch set introduces Intel FPGA BUS support in DPDK. >=20 Though opens remains, overall is OK, no objection for merge. Reviewed-by: Qi Zhang