From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 5569C58C4; Tue, 10 Jul 2018 09:57:41 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jul 2018 00:57:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,333,1526367600"; d="scan'208";a="65641557" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga002.fm.intel.com with ESMTP; 10 Jul 2018 00:57:34 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 10 Jul 2018 00:57:33 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 10 Jul 2018 00:57:33 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.100]) by shsmsx102.ccr.corp.intel.com ([169.254.2.124]) with mapi id 14.03.0319.002; Tue, 10 Jul 2018 15:57:31 +0800 From: "Zhang, Qi Z" To: "Li, Xiaoyun" , "Xing, Beilei" CC: "dev@dpdk.org" , "Li, Xiaoyun" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] net/i40e: fix link speed issue Thread-Index: AQHUEcXjAYifWe1py0yk0B//aqOfFKSIIYeg Date: Tue, 10 Jul 2018 07:57:31 +0000 Message-ID: <039ED4275CED7440929022BC67E7061153257C4C@SHSMSX103.ccr.corp.intel.com> References: <1530508681-50504-1-git-send-email-xiaoyun.li@intel.com> In-Reply-To: <1530508681-50504-1-git-send-email-xiaoyun.li@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNzk5MGI5ZDctM2NiYS00MmY2LWExMDEtYTg0ZDkzNDk5ZWU4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiaktaQmxzK25IV3pkU3d0WDd3SG95M2Q2aFF5WndvbFJQVVJFdWFaXC9TNGVYTm00cklzUVwvenRqb2xmcmZ2S3pJIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/i40e: fix link speed issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jul 2018 07:57:42 -0000 Hi Xiaoyun: > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Xiaoyun Li > Sent: Monday, July 2, 2018 1:18 PM > To: Xing, Beilei > Cc: dev@dpdk.org; Li, Xiaoyun ; stable@dpdk.org > Subject: [dpdk-dev] [PATCH] net/i40e: fix link speed issue >=20 > When link needs to go up, I40E_AQ_PHY_AN_ENABLED is always be set in > DPDK. > So all speeds are always set. This causes speed config never works. >=20 > This patch fixes this issue and only allows to set available speeds. If l= ink needs > to go up and speed setting is not supported, it will print warning and se= t > default available speeds. And when link needs to go down, link speed fiel= d > should be set to non-zero to avoid link down issue when binding back to k= ernel > driver. >=20 > Fixes: ca7e599d4506 ("net/i40e: fix link management") > Fixes: 1bb8f661168d ("net/i40e: fix link down and negotiation") > Cc: stable@dpdk.org >=20 > Signed-off-by: Xiaoyun Li > --- > drivers/net/i40e/i40e_ethdev.c | 58 > ++++++++++++++++++++++++++---------------- > 1 file changed, 36 insertions(+), 22 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethde= v.c > index 13c5d32..272a975 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -2026,27 +2026,38 @@ i40e_phy_conf_link(struct i40e_hw *hw, > struct i40e_aq_get_phy_abilities_resp phy_ab; > struct i40e_aq_set_phy_config phy_conf; > enum i40e_aq_phy_type cnt; > + uint8_t avail_speed; > uint32_t phy_type_mask =3D 0; >=20 > const uint8_t mask =3D I40E_AQ_PHY_FLAG_PAUSE_TX | > I40E_AQ_PHY_FLAG_PAUSE_RX | > I40E_AQ_PHY_FLAG_PAUSE_RX | > I40E_AQ_PHY_FLAG_LOW_POWER; > - const uint8_t advt =3D I40E_LINK_SPEED_40GB | > - I40E_LINK_SPEED_25GB | > - I40E_LINK_SPEED_10GB | > - I40E_LINK_SPEED_1GB | > - I40E_LINK_SPEED_100MB; > int ret =3D -ENOTSUP; >=20 > + /* To get phy capabilities of available speeds. */ > + status =3D i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, > + NULL); > + if (status) { > + PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n", > + status); > + return ret; > + } > + avail_speed =3D phy_ab.link_speed; >=20 > + /* To get the current phy config. */ > status =3D i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab, > NULL); > - if (status) > + if (status) { > + PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n", > + status); > return ret; > + } >=20 > - /* If link already up, no need to set up again */ > - if (is_up && phy_ab.phy_type !=3D 0) > + /* If link needs to go up and its speed values are OK, no need > + * to set up again. > + */ > + if (is_up && phy_ab.phy_type !=3D 0 && phy_ab.link_speed !=3D 0) > return I40E_SUCCESS; Why phy_ab.link_speed !=3D0 means speed values are OK? What if dev->data->dev_conf->link_speed !=3D ETH_LINK_SPEED_AUTONEG and use= r want a specific speed? Should we also add "&& capability & I40E_AQ_PHY_AN_ENABLED" here ? >=20 > memset(&phy_conf, 0, sizeof(phy_conf)); @@ -2055,15 +2066,17 @@ > i40e_phy_conf_link(struct i40e_hw *hw, > abilities &=3D ~mask; > abilities |=3D phy_ab.abilities & mask; >=20 > - /* update ablities and speed */ > - if (abilities & I40E_AQ_PHY_AN_ENABLED) > - phy_conf.link_speed =3D advt; > - else > - phy_conf.link_speed =3D is_up ? force_speed : phy_ab.link_speed; > - > phy_conf.abilities =3D abilities; >=20 > - > + /* If link needs to go up, but the force speed is not supported, > + * Warn users and config the default available speeds. > + */ > + if (is_up && !(force_speed & avail_speed)) { > + PMD_DRV_LOG(WARNING, "Invalid speed setting, set to > default!\n"); > + phy_conf.link_speed =3D avail_speed; > + } else { > + phy_conf.link_speed =3D is_up ? force_speed : avail_speed; > + } >=20 > /* To enable link, phy_type mask needs to include each type */ > for (cnt =3D I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++) @@ > -2099,6 +2112,14 @@ i40e_apply_link_speed(struct rte_eth_dev *dev) > struct i40e_hw *hw =3D > I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); > struct rte_eth_conf *conf =3D &dev->data->dev_conf; >=20 > + if (conf->link_speeds =3D=3D ETH_LINK_SPEED_AUTONEG) { > + conf->link_speeds =3D ETH_LINK_SPEED_40G | > + ETH_LINK_SPEED_25G | > + ETH_LINK_SPEED_20G | > + ETH_LINK_SPEED_10G | > + ETH_LINK_SPEED_1G | > + ETH_LINK_SPEED_100M; > + } > speed =3D i40e_parse_link_speeds(conf->link_speeds); > abilities |=3D I40E_AQ_PHY_ENABLE_ATOMIC_LINK; > if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED)) @@ -2220,13 +2241,6 > @@ i40e_dev_start(struct rte_eth_dev *dev) > } >=20 > /* Apply link configure */ > - if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M | > - ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G | > - ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | > - ETH_LINK_SPEED_40G)) { > - PMD_DRV_LOG(ERR, "Invalid link setting"); > - goto err_up; > - } > ret =3D i40e_apply_link_speed(dev); > if (I40E_SUCCESS !=3D ret) { > PMD_DRV_LOG(ERR, "Fail to apply link setting"); > -- > 2.7.4