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From: "Zhang, Qi Z" <qi.z.zhang@intel.com>
To: "Wu, Yanglong" <yanglong.wu@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: "Wu, Jingjing" <jingjing.wu@intel.com>,
	"Byrne, Stephen1" <stephen1.byrne@intel.com>
Subject: Re: [dpdk-dev] [PATCH] net/ixgbe: fix TDH register setting issue
Date: Fri, 16 Nov 2018 19:51:34 +0000	[thread overview]
Message-ID: <039ED4275CED7440929022BC67E70611532E518D@SHSMSX103.ccr.corp.intel.com> (raw)
In-Reply-To: <20181116023220.114517-1-yanglong.wu@intel.com>

Hi Yanglong:

> -----Original Message-----
> From: Wu, Yanglong
> Sent: Thursday, November 15, 2018 6:32 PM
> To: dev@dpdk.org
> Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>;
> Byrne, Stephen1 <stephen1.byrne@intel.com>; Wu, Yanglong
> <yanglong.wu@intel.com>
> Subject: [PATCH] net/ixgbe: fix TDH register setting issue
> 
> The only time that software should write to the TDH register is after a reset
> (hardware reset or CTRL.RST) and before enabling the transmit function
> (TXDCTL.ENABLE).
> If software were to write to this register while the transmit function was
> enabled, the on-chip descriptor buffers might be invalidated and the hardware
> could become confused.
> 
> Fixes: a8cdaf0964f7 ("net/ixgbe: remove redundant queue id checks")

I try to understand why this patch is going to fix above commit. 
seems the commit didn't change the register write order, and even if we go much early I saw the TDH register is always be written after TXDCTL.ENABL.
Did I missed something?
btw, I'm also curious why only TDH matters but TDT does not.

> Signed-off-by: Yanglong Wu <yanglong.wu@intel.com>
> ---
>  drivers/net/ixgbe/ixgbe_rxtx.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
> index 2f0262ae1..ddc7efa87 100644
> --- a/drivers/net/ixgbe/ixgbe_rxtx.c
> +++ b/drivers/net/ixgbe/ixgbe_rxtx.c
> @@ -5264,6 +5264,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev,
> uint16_t tx_queue_id)
>  	hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
> 
>  	txq = dev->data->tx_queues[tx_queue_id];
> +	IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
>  	txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
>  	txdctl |= IXGBE_TXDCTL_ENABLE;
>  	IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); @@
> -5281,7 +5282,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev,
> uint16_t tx_queue_id)
>  				tx_queue_id);
>  	}
>  	rte_wmb();
> -	IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
>  	IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
>  	dev->data->tx_queue_state[tx_queue_id] =
> RTE_ETH_QUEUE_STATE_STARTED;
> 
> --
> 2.11.0

  reply	other threads:[~2018-11-16 19:51 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-16  2:32 Yanglong Wu
2018-11-16 19:51 ` Zhang, Qi Z [this message]
2018-11-20  2:11   ` Wu, Yanglong
2018-11-20  6:02     ` Zhang, Qi Z
2018-11-20  5:59 ` [dpdk-dev] [PATCH v2] " Yanglong Wu
2018-11-20 19:49   ` Zhang, Qi Z

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