From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 964A947CE for ; Fri, 16 Nov 2018 20:51:38 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Nov 2018 11:51:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,241,1539673200"; d="scan'208";a="96907379" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by FMSMGA003.fm.intel.com with ESMTP; 16 Nov 2018 11:51:37 -0800 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 16 Nov 2018 11:51:37 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 16 Nov 2018 11:51:36 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.161]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.199]) with mapi id 14.03.0415.000; Sat, 17 Nov 2018 03:51:34 +0800 From: "Zhang, Qi Z" To: "Wu, Yanglong" , "dev@dpdk.org" CC: "Wu, Jingjing" , "Byrne, Stephen1" Thread-Topic: [PATCH] net/ixgbe: fix TDH register setting issue Thread-Index: AQHUfVYAaRJ5faBoZkiG6bFQDa+o36VSy73A Date: Fri, 16 Nov 2018 19:51:34 +0000 Message-ID: <039ED4275CED7440929022BC67E70611532E518D@SHSMSX103.ccr.corp.intel.com> References: <20181116023220.114517-1-yanglong.wu@intel.com> In-Reply-To: <20181116023220.114517-1-yanglong.wu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiM2I2YmNiMGQtZGJiNi00N2ZhLTkxNTEtYWU5YzJlNmI5MzYzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiUXo2RTBNSUJ3QVpPRVwvR1FcL2dVSGNteVFhd2RjQTRIMGp6eThNYWh1QytXb3RiUWVjZjY3STNzZnFMZ2VmamFHIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/ixgbe: fix TDH register setting issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Nov 2018 19:51:39 -0000 Hi Yanglong: > -----Original Message----- > From: Wu, Yanglong > Sent: Thursday, November 15, 2018 6:32 PM > To: dev@dpdk.org > Cc: Zhang, Qi Z ; Wu, Jingjing ; > Byrne, Stephen1 ; Wu, Yanglong > > Subject: [PATCH] net/ixgbe: fix TDH register setting issue >=20 > The only time that software should write to the TDH register is after a r= eset > (hardware reset or CTRL.RST) and before enabling the transmit function > (TXDCTL.ENABLE). > If software were to write to this register while the transmit function wa= s > enabled, the on-chip descriptor buffers might be invalidated and the hard= ware > could become confused. >=20 > Fixes: a8cdaf0964f7 ("net/ixgbe: remove redundant queue id checks") I try to understand why this patch is going to fix above commit.=20 seems the commit didn't change the register write order, and even if we go = much early I saw the TDH register is always be written after TXDCTL.ENABL. Did I missed something? btw, I'm also curious why only TDH matters but TDT does not. > Signed-off-by: Yanglong Wu > --- > drivers/net/ixgbe/ixgbe_rxtx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxt= x.c > index 2f0262ae1..ddc7efa87 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -5264,6 +5264,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, > uint16_t tx_queue_id) > hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); >=20 > txq =3D dev->data->tx_queues[tx_queue_id]; > + IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); > txdctl =3D IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); > txdctl |=3D IXGBE_TXDCTL_ENABLE; > IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); @@ > -5281,7 +5282,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, > uint16_t tx_queue_id) > tx_queue_id); > } > rte_wmb(); > - IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); > IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); > dev->data->tx_queue_state[tx_queue_id] =3D > RTE_ETH_QUEUE_STATE_STARTED; >=20 > -- > 2.11.0