* [dpdk-dev] [PATCH] net/ixgbe: fix TDH register setting issue
@ 2018-11-16 2:32 Yanglong Wu
2018-11-16 19:51 ` Zhang, Qi Z
2018-11-20 5:59 ` [dpdk-dev] [PATCH v2] " Yanglong Wu
0 siblings, 2 replies; 6+ messages in thread
From: Yanglong Wu @ 2018-11-16 2:32 UTC (permalink / raw)
To: dev; +Cc: qi.z.zhang, jingjing.wu, stephen1.byrne, Yanglong Wu
The only time that software should write to the TDH register
is after a reset (hardware reset or CTRL.RST) and
before enabling the transmit function (TXDCTL.ENABLE).
If software were to write to this register while the transmit
function was enabled, the on-chip descriptor buffers might
be invalidated and the hardware could become confused.
Fixes: a8cdaf0964f7 ("net/ixgbe: remove redundant queue id checks")
Signed-off-by: Yanglong Wu <yanglong.wu@intel.com>
---
drivers/net/ixgbe/ixgbe_rxtx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 2f0262ae1..ddc7efa87 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5264,6 +5264,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
txq = dev->data->tx_queues[tx_queue_id];
+ IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
txdctl |= IXGBE_TXDCTL_ENABLE;
IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
@@ -5281,7 +5282,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
tx_queue_id);
}
rte_wmb();
- IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
--
2.11.0
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [dpdk-dev] [PATCH] net/ixgbe: fix TDH register setting issue 2018-11-16 2:32 [dpdk-dev] [PATCH] net/ixgbe: fix TDH register setting issue Yanglong Wu @ 2018-11-16 19:51 ` Zhang, Qi Z 2018-11-20 2:11 ` Wu, Yanglong 2018-11-20 5:59 ` [dpdk-dev] [PATCH v2] " Yanglong Wu 1 sibling, 1 reply; 6+ messages in thread From: Zhang, Qi Z @ 2018-11-16 19:51 UTC (permalink / raw) To: Wu, Yanglong, dev; +Cc: Wu, Jingjing, Byrne, Stephen1 Hi Yanglong: > -----Original Message----- > From: Wu, Yanglong > Sent: Thursday, November 15, 2018 6:32 PM > To: dev@dpdk.org > Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>; > Byrne, Stephen1 <stephen1.byrne@intel.com>; Wu, Yanglong > <yanglong.wu@intel.com> > Subject: [PATCH] net/ixgbe: fix TDH register setting issue > > The only time that software should write to the TDH register is after a reset > (hardware reset or CTRL.RST) and before enabling the transmit function > (TXDCTL.ENABLE). > If software were to write to this register while the transmit function was > enabled, the on-chip descriptor buffers might be invalidated and the hardware > could become confused. > > Fixes: a8cdaf0964f7 ("net/ixgbe: remove redundant queue id checks") I try to understand why this patch is going to fix above commit. seems the commit didn't change the register write order, and even if we go much early I saw the TDH register is always be written after TXDCTL.ENABL. Did I missed something? btw, I'm also curious why only TDH matters but TDT does not. > Signed-off-by: Yanglong Wu <yanglong.wu@intel.com> > --- > drivers/net/ixgbe/ixgbe_rxtx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c > index 2f0262ae1..ddc7efa87 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -5264,6 +5264,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, > uint16_t tx_queue_id) > hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > txq = dev->data->tx_queues[tx_queue_id]; > + IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); > txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); > txdctl |= IXGBE_TXDCTL_ENABLE; > IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); @@ > -5281,7 +5282,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, > uint16_t tx_queue_id) > tx_queue_id); > } > rte_wmb(); > - IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); > IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); > dev->data->tx_queue_state[tx_queue_id] = > RTE_ETH_QUEUE_STATE_STARTED; > > -- > 2.11.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [dpdk-dev] [PATCH] net/ixgbe: fix TDH register setting issue 2018-11-16 19:51 ` Zhang, Qi Z @ 2018-11-20 2:11 ` Wu, Yanglong 2018-11-20 6:02 ` Zhang, Qi Z 0 siblings, 1 reply; 6+ messages in thread From: Wu, Yanglong @ 2018-11-20 2:11 UTC (permalink / raw) To: Zhang, Qi Z, dev; +Cc: Wu, Jingjing, Byrne, Stephen1 Hi, qi I don't understand why dose this patch not change register write order. THD is write before TXDCTL.ENABL. The Intel 82599 data sheet (https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82599-10-gbe-controller-datasheet.pdf, §8.2.3.9.8) states that "The only time that software should write to [the TDH] register is after a reset (hardware reset or CTRL.RST) and before enabling the transmit function (TXDCTL.ENABLE). If software were to write to this register while the transmit function was enabled, the on-chip descriptor buffers might be invalidated and the hardware could become confused". Regard yanglong -----Original Message----- From: Zhang, Qi Z Sent: Saturday, November 17, 2018 3:52 AM To: Wu, Yanglong <yanglong.wu@intel.com>; dev@dpdk.org Cc: Wu, Jingjing <jingjing.wu@intel.com>; Byrne, Stephen1 <stephen1.byrne@intel.com> Subject: RE: [PATCH] net/ixgbe: fix TDH register setting issue Hi Yanglong: > -----Original Message----- > From: Wu, Yanglong > Sent: Thursday, November 15, 2018 6:32 PM > To: dev@dpdk.org > Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Wu, Jingjing > <jingjing.wu@intel.com>; Byrne, Stephen1 <stephen1.byrne@intel.com>; > Wu, Yanglong <yanglong.wu@intel.com> > Subject: [PATCH] net/ixgbe: fix TDH register setting issue > > The only time that software should write to the TDH register is after > a reset (hardware reset or CTRL.RST) and before enabling the transmit > function (TXDCTL.ENABLE). > If software were to write to this register while the transmit function > was enabled, the on-chip descriptor buffers might be invalidated and > the hardware could become confused. > > Fixes: a8cdaf0964f7 ("net/ixgbe: remove redundant queue id checks") I try to understand why this patch is going to fix above commit. seems the commit didn't change the register write order, and even if we go much early I saw the TDH register is always be written after TXDCTL.ENABL. Did I missed something? btw, I'm also curious why only TDH matters but TDT does not. > Signed-off-by: Yanglong Wu <yanglong.wu@intel.com> > --- > drivers/net/ixgbe/ixgbe_rxtx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c > b/drivers/net/ixgbe/ixgbe_rxtx.c index 2f0262ae1..ddc7efa87 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -5264,6 +5264,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev > *dev, uint16_t tx_queue_id) > hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > txq = dev->data->tx_queues[tx_queue_id]; > + IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); > txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); > txdctl |= IXGBE_TXDCTL_ENABLE; > IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); @@ > -5281,7 +5282,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, > uint16_t tx_queue_id) > tx_queue_id); > } > rte_wmb(); > - IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); > IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); > dev->data->tx_queue_state[tx_queue_id] = > RTE_ETH_QUEUE_STATE_STARTED; > > -- > 2.11.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [dpdk-dev] [PATCH] net/ixgbe: fix TDH register setting issue 2018-11-20 2:11 ` Wu, Yanglong @ 2018-11-20 6:02 ` Zhang, Qi Z 0 siblings, 0 replies; 6+ messages in thread From: Zhang, Qi Z @ 2018-11-20 6:02 UTC (permalink / raw) To: Wu, Yanglong, dev; +Cc: Wu, Jingjing, Byrne, Stephen1 > -----Original Message----- > From: Wu, Yanglong > Sent: Monday, November 19, 2018 6:12 PM > To: Zhang, Qi Z <qi.z.zhang@intel.com>; dev@dpdk.org > Cc: Wu, Jingjing <jingjing.wu@intel.com>; Byrne, Stephen1 > <stephen1.byrne@intel.com> > Subject: RE: [PATCH] net/ixgbe: fix TDH register setting issue > > Hi, qi > I don't understand why dose this patch not change register write order. > THD is write before TXDCTL.ENABL. > > The Intel 82599 data sheet > (https://www.intel.com/content/dam/www/public/us/en/documents/datashe > ets/82599-10-gbe-controller-datasheet.pdf, §8.2.3.9.8) states that "The only > time that software should write to [the TDH] register is after a reset (hardware > reset or CTRL.RST) and before enabling the transmit function (TXDCTL.ENABLE). > If software were to write to this register while the transmit function was > enabled, the on-chip descriptor buffers might be invalidated and the hardware > could become confused". OK got it, I think you can use below commit as to fix. commit 029fd06d40fa8cff7f562dc85d7cc4609d5c91fb Author: Ouyang Changchun <changchun.ouyang@intel.com> Date: Wed May 28 16:06:37 2014 +0800 ixgbe: queue start and stop This patch implements queue start and stop functionality in IXGBE PMD; it also enable hardware loopback for VMDQ mode in IXGBE PMD. Signed-off-by: Ouyang Changchun <changchun.ouyang@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com> Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com> > > Regard > yanglong > > -----Original Message----- > From: Zhang, Qi Z > Sent: Saturday, November 17, 2018 3:52 AM > To: Wu, Yanglong <yanglong.wu@intel.com>; dev@dpdk.org > Cc: Wu, Jingjing <jingjing.wu@intel.com>; Byrne, Stephen1 > <stephen1.byrne@intel.com> > Subject: RE: [PATCH] net/ixgbe: fix TDH register setting issue > > Hi Yanglong: > > > -----Original Message----- > > From: Wu, Yanglong > > Sent: Thursday, November 15, 2018 6:32 PM > > To: dev@dpdk.org > > Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Wu, Jingjing > > <jingjing.wu@intel.com>; Byrne, Stephen1 <stephen1.byrne@intel.com>; > > Wu, Yanglong <yanglong.wu@intel.com> > > Subject: [PATCH] net/ixgbe: fix TDH register setting issue > > > > The only time that software should write to the TDH register is after > > a reset (hardware reset or CTRL.RST) and before enabling the transmit > > function (TXDCTL.ENABLE). > > If software were to write to this register while the transmit function > > was enabled, the on-chip descriptor buffers might be invalidated and > > the hardware could become confused. > > > > Fixes: a8cdaf0964f7 ("net/ixgbe: remove redundant queue id checks") > > I try to understand why this patch is going to fix above commit. > seems the commit didn't change the register write order, and even if we go > much early I saw the TDH register is always be written after TXDCTL.ENABL. > Did I missed something? > btw, I'm also curious why only TDH matters but TDT does not. > > > Signed-off-by: Yanglong Wu <yanglong.wu@intel.com> > > --- > > drivers/net/ixgbe/ixgbe_rxtx.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c > > b/drivers/net/ixgbe/ixgbe_rxtx.c index 2f0262ae1..ddc7efa87 100644 > > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > > @@ -5264,6 +5264,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev > > *dev, uint16_t tx_queue_id) > > hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > > > txq = dev->data->tx_queues[tx_queue_id]; > > + IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); > > txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); > > txdctl |= IXGBE_TXDCTL_ENABLE; > > IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); @@ > > -5281,7 +5282,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, > > uint16_t tx_queue_id) > > tx_queue_id); > > } > > rte_wmb(); > > - IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); > > IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); > > dev->data->tx_queue_state[tx_queue_id] = > > RTE_ETH_QUEUE_STATE_STARTED; > > > > -- > > 2.11.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [dpdk-dev] [PATCH v2] net/ixgbe: fix TDH register setting issue 2018-11-16 2:32 [dpdk-dev] [PATCH] net/ixgbe: fix TDH register setting issue Yanglong Wu 2018-11-16 19:51 ` Zhang, Qi Z @ 2018-11-20 5:59 ` Yanglong Wu 2018-11-20 19:49 ` Zhang, Qi Z 1 sibling, 1 reply; 6+ messages in thread From: Yanglong Wu @ 2018-11-20 5:59 UTC (permalink / raw) To: dev; +Cc: qi.z.zhang, jingjing.wu, Yanglong Wu The only time that software should write to the TDH register is after a reset (hardware reset or CTRL.RST) and before enabling the transmit function (TXDCTL.ENABLE). If software were to write to this register while the transmit function was enabled, the on-chip descriptor buffers might be invalidated and the hardware could become confused. cc stable@dpdk.org Signed-off-by: Yanglong Wu <yanglong.wu@intel.com> --- v2: change fix commit --- drivers/net/ixgbe/ixgbe_rxtx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 2f0262ae1..ddc7efa87 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -5264,6 +5264,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); txq = dev->data->tx_queues[tx_queue_id]; + IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); txdctl |= IXGBE_TXDCTL_ENABLE; IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); @@ -5281,7 +5282,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) tx_queue_id); } rte_wmb(); - IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; -- 2.11.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [dpdk-dev] [PATCH v2] net/ixgbe: fix TDH register setting issue 2018-11-20 5:59 ` [dpdk-dev] [PATCH v2] " Yanglong Wu @ 2018-11-20 19:49 ` Zhang, Qi Z 0 siblings, 0 replies; 6+ messages in thread From: Zhang, Qi Z @ 2018-11-20 19:49 UTC (permalink / raw) To: Wu, Yanglong, dev; +Cc: Wu, Jingjing > -----Original Message----- > From: Wu, Yanglong > Sent: Monday, November 19, 2018 9:59 PM > To: dev@dpdk.org > Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>; > Wu, Yanglong <yanglong.wu@intel.com> > Subject: [PATCH v2] net/ixgbe: fix TDH register setting issue > > The only time that software should write to the TDH register is after a reset > (hardware reset or CTRL.RST) and before enabling the transmit function > (TXDCTL.ENABLE). > If software were to write to this register while the transmit function was > enabled, the on-chip descriptor buffers might be invalidated and the hardware > could become confused. > > cc stable@dpdk.org Cc: stable@dpdk.org > Signed-off-by: Yanglong Wu <yanglong.wu@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com> Applied to dpdk-next-net-intel with adding below fix line Fixes: 029fd06d40fa ("ixgbe: queue start and stop") Thanks Qi ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-11-20 19:49 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-11-16 2:32 [dpdk-dev] [PATCH] net/ixgbe: fix TDH register setting issue Yanglong Wu 2018-11-16 19:51 ` Zhang, Qi Z 2018-11-20 2:11 ` Wu, Yanglong 2018-11-20 6:02 ` Zhang, Qi Z 2018-11-20 5:59 ` [dpdk-dev] [PATCH v2] " Yanglong Wu 2018-11-20 19:49 ` Zhang, Qi Z
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