From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id CEC3D91 for ; Tue, 20 Nov 2018 20:49:56 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Nov 2018 11:49:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,258,1539673200"; d="scan'208";a="87428562" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga007.fm.intel.com with ESMTP; 20 Nov 2018 11:49:55 -0800 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 20 Nov 2018 11:49:55 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 20 Nov 2018 11:49:55 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.161]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.102]) with mapi id 14.03.0415.000; Wed, 21 Nov 2018 03:49:52 +0800 From: "Zhang, Qi Z" To: "Wu, Yanglong" , "dev@dpdk.org" CC: "Wu, Jingjing" Thread-Topic: [PATCH v2] net/ixgbe: fix TDH register setting issue Thread-Index: AQHUgJgsM6KJG1y8c0ClQfJWq0bFR6VZErrw Date: Tue, 20 Nov 2018 19:49:52 +0000 Message-ID: <039ED4275CED7440929022BC67E70611532E8C2D@SHSMSX103.ccr.corp.intel.com> References: <20181116023220.114517-1-yanglong.wu@intel.com> <20181120055921.8209-1-yanglong.wu@intel.com> In-Reply-To: <20181120055921.8209-1-yanglong.wu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNzBlNjRlNTUtOWE2Ny00YjBjLTljODctNDEyNjE5NjU0ZTRlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiKyswdlpLK3BaTGVSeEdQXC9uYkNtZCtmTEJ0RTFsMXM5d1V5OUNBSVlUOFBibGJoenZ5dUpIdzVZSE40WU9IS3kifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] net/ixgbe: fix TDH register setting issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Nov 2018 19:49:57 -0000 > -----Original Message----- > From: Wu, Yanglong > Sent: Monday, November 19, 2018 9:59 PM > To: dev@dpdk.org > Cc: Zhang, Qi Z ; Wu, Jingjing ; > Wu, Yanglong > Subject: [PATCH v2] net/ixgbe: fix TDH register setting issue >=20 > The only time that software should write to the TDH register is after a r= eset > (hardware reset or CTRL.RST) and before enabling the transmit function > (TXDCTL.ENABLE). > If software were to write to this register while the transmit function wa= s > enabled, the on-chip descriptor buffers might be invalidated and the hard= ware > could become confused. >=20 > cc stable@dpdk.org Cc: stable@dpdk.org > Signed-off-by: Yanglong Wu Acked-by: Qi Zhang Applied to dpdk-next-net-intel with adding below fix line Fixes: 029fd06d40fa ("ixgbe: queue start and stop") Thanks Qi