From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C780A04F9; Thu, 26 Dec 2019 02:50:38 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C70511BF6F; Thu, 26 Dec 2019 02:50:37 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 67E621BF30; Thu, 26 Dec 2019 02:50:35 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Dec 2019 17:50:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,357,1571727600"; d="scan'208";a="223487554" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga001.fm.intel.com with ESMTP; 25 Dec 2019 17:50:34 -0800 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 25 Dec 2019 17:50:34 -0800 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 25 Dec 2019 17:50:33 -0800 Received: from shsmsx105.ccr.corp.intel.com ([169.254.11.72]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.71]) with mapi id 14.03.0439.000; Thu, 26 Dec 2019 09:50:32 +0800 From: "Zhang, Qi Z" To: "Li, Xiaoyun" , "Xing, Beilei" , "Ye, Xiaolong" , "Loftus, Ciara" , "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH v2] net/i40e: fix TSO pkt exceeds allowed buf size issue Thread-Index: AQHVuwFeEaCR0Ahl6UuWIjkcN5d58afLpfJg Date: Thu, 26 Dec 2019 01:50:31 +0000 Message-ID: <039ED4275CED7440929022BC67E7061153DF389B@SHSMSX105.ccr.corp.intel.com> References: <20191225085532.19520-1-xiaoyun.li@intel.com> In-Reply-To: <20191225085532.19520-1-xiaoyun.li@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjdmMjI1MjItOTE5MS00MGE1LWJjNWYtOTdiZjY4MzJhMTcxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoibXpqNkxmYzFqSzlZcUxzRkxxZVl2TnF3NHFrNkhnMmhpVUtpRDFUeVNqYWdzVFhqajZ5eDRSNVRVWDBNTlpMNyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] net/i40e: fix TSO pkt exceeds allowed buf size issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" HI Xiaoyun: Overall looks good to me, some minor capture inline > -----Original Message----- > From: Li, Xiaoyun > Sent: Wednesday, December 25, 2019 4:56 PM > To: Zhang, Qi Z ; Xing, Beilei ; > Ye, Xiaolong ; Loftus, Ciara ; > dev@dpdk.org > Cc: Li, Xiaoyun ; stable@dpdk.org > Subject: [PATCH v2] net/i40e: fix TSO pkt exceeds allowed buf size issue >=20 > Hardware limits that max buffer size per tx descriptor should be (16K-1)B= . So > when TSO enabled, the mbuf data size may exceed the limit and cause > malicious behaviour to the NIC. This patch fixes this issue by using more= tx Behavior > descs for this kind of large buffer. >=20 > Fixes: 4861cde46116 ("i40e: new poll mode driver") > Cc: stable@dpdk.org >=20 > Signed-off-by: Xiaoyun Li > --- > v2: > * Each pkt can have several segments so the needed tx descs should sum > * all segments up. > --- > drivers/net/i40e/i40e_rxtx.c | 44 +++++++++++++++++++++++++++++++++++- > 1 file changed, 43 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c = index > 17dc8c78f..ce95d8c20 100644 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -989,6 +989,23 @@ i40e_set_tso_ctx(struct rte_mbuf *mbuf, union > i40e_tx_offload tx_offload) > return ctx_desc; > } >=20 > +/* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */ > +#define I40E_MAX_DATA_PER_TXD (16 * 1024 - 1) Since this is limited by the 14 bit buffer size on Rx descriptor. Is it better to reuse exist macro to define the max buf size? #define I40E_MAX_DATA_PER_TXD \ I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT Regards Qi > +/* Calculate the number of TX descriptors needed for each pkt */ static > +inline uint16_t i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt) { > + struct rte_mbuf *txd =3D tx_pkt; > + uint16_t count =3D 0; > + > + while (txd !=3D NULL) { > + count +=3D DIV_ROUND_UP(txd->data_len, > I40E_MAX_DATA_PER_TXD); > + txd =3D txd->next; > + } > + > + return count; > +} > + > uint16_t > i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pk= ts) > { @@ -1046,8 +1063,15 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf > **tx_pkts, uint16_t nb_pkts) > * The number of descriptors that must be allocated for > * a packet equals to the number of the segments of that > * packet plus 1 context descriptor if needed. > + * Recalculate the needed tx descs when TSO enabled in case > + * the mbuf data size exceeds max data size that hw allows > + * per tx desc. > */ > - nb_used =3D (uint16_t)(tx_pkt->nb_segs + nb_ctx); > + if (ol_flags & PKT_TX_TCP_SEG) > + nb_used =3D (uint16_t)(i40e_calc_pkt_desc(tx_pkt) + > + nb_ctx); > + else > + nb_used =3D (uint16_t)(tx_pkt->nb_segs + nb_ctx); > tx_last =3D (uint16_t)(tx_id + nb_used - 1); >=20 > /* Circular ring */ > @@ -1160,6 +1184,24 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf > **tx_pkts, uint16_t nb_pkts) > slen =3D m_seg->data_len; > buf_dma_addr =3D rte_mbuf_data_iova(m_seg); >=20 > + while ((ol_flags & PKT_TX_TCP_SEG) && > + unlikely(slen > I40E_MAX_DATA_PER_TXD)) { > + txd->buffer_addr =3D > + rte_cpu_to_le_64(buf_dma_addr); > + txd->cmd_type_offset_bsz =3D > + i40e_build_ctob(td_cmd, > + td_offset, I40E_MAX_DATA_PER_TXD, > + td_tag); > + > + buf_dma_addr +=3D I40E_MAX_DATA_PER_TXD; > + slen -=3D I40E_MAX_DATA_PER_TXD; > + > + txe->last_id =3D tx_last; > + tx_id =3D txe->next_id; > + txe =3D txn; > + txd =3D &txr[tx_id]; > + txn =3D &sw_ring[txe->next_id]; > + } > PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n" > "buf_dma_addr: %#"PRIx64";\n" > "td_cmd: %#x;\n" > -- > 2.17.1