From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A2609A0583; Thu, 19 Mar 2020 02:46:14 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CF9762C28; Thu, 19 Mar 2020 02:46:13 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 680653B5 for ; Thu, 19 Mar 2020 02:46:10 +0100 (CET) IronPort-SDR: TVBYOMye4DIQD54gfSD6lMgeotNUgIDBWLJsgScljk80aTCsXOpjqow360sRX14CKrt2zQPCPt /bZfgqJykzJw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2020 18:46:09 -0700 IronPort-SDR: AIPOfqaCnTjvErsw/+xScpOmraFIXiNJ0RIBRGeU5eMyFVK5fXw0oMCE4XmXBV+lBjxACmQOGq zPDfrWbTu1Rw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,569,1574150400"; d="scan'208";a="263577881" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga002.jf.intel.com with ESMTP; 18 Mar 2020 18:46:09 -0700 Received: from fmsmsx161.amr.corp.intel.com (10.18.125.9) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 18 Mar 2020 18:46:08 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX161.amr.corp.intel.com (10.18.125.9) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 18 Mar 2020 18:46:08 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.137]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.206]) with mapi id 14.03.0439.000; Thu, 19 Mar 2020 09:46:05 +0800 From: "Zhang, Qi Z" To: "Su, Simei" , "Ye, Xiaolong" CC: "dev@dpdk.org" , "Cao, Yahui" , "Wu, Jingjing" Thread-Topic: [PATCH 2/5] net/iavf: add support for FDIR GTPU Thread-Index: AQHV/Og1RIlqjIrtyUKZ9i80VVeOPahPJL3Q Date: Thu, 19 Mar 2020 01:46:04 +0000 Message-ID: <039ED4275CED7440929022BC67E70611547E39E0@SHSMSX103.ccr.corp.intel.com> References: <1584510121-377747-1-git-send-email-simei.su@intel.com> <1584510121-377747-3-git-send-email-simei.su@intel.com> In-Reply-To: <1584510121-377747-3-git-send-email-simei.su@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 2/5] net/iavf: add support for FDIR GTPU X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Su, Simei > Sent: Wednesday, March 18, 2020 1:42 PM > To: Ye, Xiaolong ; Zhang, Qi Z > Cc: dev@dpdk.org; Cao, Yahui ; Wu, Jingjing > ; Su, Simei > Subject: [PATCH 2/5] net/iavf: add support for FDIR GTPU >=20 > This patch enables GTPU pattern for RTE_FLOW. The comment is misleading, the GTPU pattern for rte_flow is already enabled= in other patch,=20 this patch actually add GTPU flow filter support in FDIR. >=20 > Signed-off-by: Simei Su > --- > drivers/net/iavf/iavf_fdir.c | 67 > ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 67 insertions(+) >=20 > diff --git a/drivers/net/iavf/iavf_fdir.c b/drivers/net/iavf/iavf_fdir.c = index > dd321ba..ad100c8 100644 > --- a/drivers/net/iavf/iavf_fdir.c > +++ b/drivers/net/iavf/iavf_fdir.c > @@ -67,6 +67,14 @@ > IAVF_INSET_IPV6_TC | IAVF_INSET_IPV6_HOP_LIMIT | \ > IAVF_INSET_SCTP_SRC_PORT | IAVF_INSET_SCTP_DST_PORT) >=20 > +#define IAVF_FDIR_INSET_GTPU (\ > + IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \ > + IAVF_INSET_GTPU_TEID) > + > +#define IAVF_FDIR_INSET_GTPU_EH (\ > + IAVF_INSET_IPV4_SRC | IAVF_INSET_IPV4_DST | \ > + IAVF_INSET_GTPU_TEID | IAVF_INSET_GTPU_QFI) > + > static struct iavf_pattern_match_item iavf_fdir_pattern[] =3D { > {iavf_pattern_ethertype, IAVF_FDIR_INSET_ETH, > IAVF_INSET_NONE}, > {iavf_pattern_eth_ipv4, IAVF_FDIR_INSET_ETH_IPV4, > IAVF_INSET_NONE}, > @@ -77,6 +85,8 @@ > {iavf_pattern_eth_ipv6_udp, IAVF_FDIR_INSET_ETH_IPV6_UDP, > IAVF_INSET_NONE}, > {iavf_pattern_eth_ipv6_tcp, IAVF_FDIR_INSET_ETH_IPV6_TCP, > IAVF_INSET_NONE}, > {iavf_pattern_eth_ipv6_sctp, > IAVF_FDIR_INSET_ETH_IPV6_SCTP, IAVF_INSET_NONE}, > + {iavf_pattern_eth_ipv4_gtpu, IAVF_FDIR_INSET_GTPU, > IAVF_INSET_NONE}, > + {iavf_pattern_eth_ipv4_gtpu_eh, IAVF_FDIR_INSET_GTPU_EH, > IAVF_INSET_NONE}, > }; >=20 > static struct iavf_flow_parser iavf_fdir_parser; @@ -360,6 +370,8 @@ > const struct rte_flow_item_udp *udp_spec, *udp_mask; > const struct rte_flow_item_tcp *tcp_spec, *tcp_mask; > const struct rte_flow_item_sctp *sctp_spec, *sctp_mask; > + const struct rte_flow_item_gtp *gtp_spec, *gtp_mask; > + const struct rte_flow_item_gtp_psc *gtp_psc_spec, *gtp_psc_mask; > uint64_t input_set =3D IAVF_INSET_NONE; >=20 > enum rte_flow_item_type next_type; > @@ -686,6 +698,61 @@ > filter->input.rule_cfg.proto_stack.count =3D ++layer; > break; >=20 > + case RTE_FLOW_ITEM_TYPE_GTPU: > + gtp_spec =3D item->spec; > + gtp_mask =3D item->mask; > + > + hdr =3D &filter->input.rule_cfg.proto_stack. > + proto_hdr[layer]; > + > + VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_IP); > + > + if (gtp_spec && gtp_mask) { > + if (gtp_mask->v_pt_rsv_flags || > + gtp_mask->msg_type || > + gtp_mask->msg_len) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > + item, "Invalid GTP mask"); > + return -rte_errno; > + } > + > + if (gtp_mask->teid =3D=3D UINT32_MAX) { > + input_set |=3D IAVF_INSET_GTPU_TEID; > + VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT( > + hdr, GTPU_IP, TEID); > + } > + > + rte_memcpy(hdr->buffer, > + gtp_spec, sizeof(*gtp_spec)); > + } > + > + filter->input.rule_cfg.proto_stack.count =3D ++layer; > + break; > + > + case RTE_FLOW_ITEM_TYPE_GTP_PSC: > + gtp_psc_spec =3D item->spec; > + gtp_psc_mask =3D item->mask; > + > + hdr =3D &filter->input.rule_cfg.proto_stack. > + proto_hdr[layer]; > + > + VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH); > + > + if (gtp_psc_spec && gtp_psc_mask) { > + if (gtp_psc_mask->qfi =3D=3D UINT8_MAX) { > + input_set |=3D IAVF_INSET_GTPU_QFI; > + VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT( > + hdr, GTPU_EH, QFI); > + } > + > + rte_memcpy(hdr->buffer, gtp_psc_spec, > + sizeof(*gtp_psc_spec)); > + } > + > + filter->input.rule_cfg.proto_stack.count =3D ++layer; > + break; > + > case RTE_FLOW_ITEM_TYPE_VOID: > break; >=20 > -- > 1.8.3.1