From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CBEF9429DB; Mon, 24 Apr 2023 14:30:31 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BB963410DE; Mon, 24 Apr 2023 14:30:31 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id CA096410D0 for ; Mon, 24 Apr 2023 14:30:29 +0200 (CEST) Received: from loongson.cn (unknown [10.20.42.90]) by gateway (Coremail) with SMTP id _____8CxvOpidkZk0wkAAA--.95S3; Mon, 24 Apr 2023 20:30:27 +0800 (CST) Received: from [10.20.42.90] (unknown [10.20.42.90]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Ax17xidkZkUMs4AA--.1940S3; Mon, 24 Apr 2023 20:30:26 +0800 (CST) Subject: Re: [PATCH 1/1] net/ixgbe: add a proper memory barrier for LoongArch To: "bibo, mao" , qiming.yang@intel.com, wenjun1.wu@intel.com Cc: dev@dpdk.org References: <20230407085041.3966259-1-zhoumin@loongson.cn> <1cfdd578-774d-f9e8-da23-4b7c29a370c5@loongson.cn> From: zhoumin Message-ID: <07cd7dde-89ca-663c-08b4-9a83b836f275@loongson.cn> Date: Mon, 24 Apr 2023 20:30:26 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID: AQAAf8Ax17xidkZkUMs4AA--.1940S3 X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjvJXoWxuF13tFWfCrWUKr17tFyftFb_yoW5GFyfpF 1kJF1jkryUGw4kJw1Iqw15Zry2yr4xXw1UG34vya4DJr4DJr1jqr1jgr909FyDtr48G3W0 vr4UZw43uFZxZr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bI8YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvEwIxGrwCYjI0SjxkI62AI1cAE67vIY487Mx AIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_ Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwI xGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8 JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxUrNtxDUUUU X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi Bibo, On Sat, Apr 22, 2023 at 8:29AM, bibo, mao wrote: > > > 在 2023/4/21 9:12, zhoumin 写道: >> On Fri, Apr 7, 2023 at 4:50PM, Min Zhou wrote: >>> Segmentation fault has been observed while running the >>> ixgbe_recv_pkts_lro() function to receive packets on the Loongson >>> 3C5000 processor which has 64 cores and 4 NUMA nodes. >>> >>> Reason is the read ordering of the status and the rest of the >>> descriptor fields in this function may not be correct on the >>> LoongArch processor. We should add rte_rmb() to ensure the read >>> ordering be correct. >>> >>> We also did the same thing in the ixgbe_recv_pkts() function. >>> >>> Signed-off-by: Min Zhou >>> --- >>>   drivers/net/ixgbe/ixgbe_rxtx.c | 6 ++++++ >>>   1 file changed, 6 insertions(+) >>> >>> diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c >>> b/drivers/net/ixgbe/ixgbe_rxtx.c >>> index c9d6ca9efe..16391a42f9 100644 >>> --- a/drivers/net/ixgbe/ixgbe_rxtx.c >>> +++ b/drivers/net/ixgbe/ixgbe_rxtx.c >>> @@ -1823,6 +1823,9 @@ ixgbe_recv_pkts(void *rx_queue, struct >>> rte_mbuf **rx_pkts, >>>           staterr = rxdp->wb.upper.status_error; >>>           if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) >>>               break; >>> +#if defined(RTE_ARCH_LOONGARCH) >>> +        rte_rmb(); >>> +#endif >>>           rxd = *rxdp; > Hi Min, > > Could you add more detailed analysis aboout the issu? Althrough rxdp > is declared as volatile, which is only in order for compiler. However > some architectures like LoongArch are weak-ordered. For this piece of > code: > >  1: staterr = rxdp->wb.upper.status_error; > Sentence 1 can be execute after sentence 1, dd indicated that packet > is ready with new value. > >  2:  rxd = *rxdp; > Sentence 2 can be execute first and get old value. > > .......Balabala > > > Regards > Bibo, Mao > Thanks for your kind comments. I have sent the v2 patch and give the more detailed analysis for the segmentation fault. Regards Min >>>           /* >>> @@ -2122,6 +2125,9 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct >>> rte_mbuf **rx_pkts, uint16_t nb_pkts, >>>           if (!(staterr & IXGBE_RXDADV_STAT_DD)) >>>               break; >>> +#if defined(RTE_ARCH_LOONGARCH) >>> +        rte_rmb(); >>> +#endif >>>           rxd = *rxdp; >>>           PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u " >> >> Kindly ping. >> >> Any comments or suggestions will be appreciated. >> >> >> Min >>