From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 52686458CD; Mon, 2 Sep 2024 11:56:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 787B7409FA; Mon, 2 Sep 2024 11:55:32 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by mails.dpdk.org (Postfix) with ESMTP id 25DAB4065C for ; Mon, 2 Sep 2024 11:55:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725270911; x=1756806911; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cOT1xIb/MFEg5yhJ/OD1qx7rZ/T8U/wjJak13tRDPcA=; b=Ci6Hdk1FN0LoTVVqG8nzKfI3/hEaH8uzCYfSJZVG4iOPKqAyhTeS+Gfu gPIovIM/dnMWBvXC8qmNkwNsmYYG4NSlN9RHZ8jQ5DvOTEHTX842MPxk9 PD0WBya6W2mhKPZOQKnoi36CNVSWrNykM2482LN3Elz2N7bTOqRCTpiGf ujHkuBH8dMtuzNUlh5CUG6N224Q7xjnNxqLbxDPCj0ATjssuWL5no1Zfn lcvNpflmJMUGMs9wIrNV/Hecpt5AyYGe7T7qa14pMCP76Pj1xHel/ODTH rn5Cs0QTmkltvSjna6vi7GIargOseV6A0uYoN3/sbR9hI7GqU6AalsSs1 Q==; X-CSE-ConnectionGUID: B9QmD89pTaCaoIm30cuOUQ== X-CSE-MsgGUID: izoJL2rMQnWK9+34gfLKow== X-IronPort-AV: E=McAfee;i="6700,10204,11182"; a="26747213" X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="26747213" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2024 02:55:10 -0700 X-CSE-ConnectionGUID: y9vvwvr+Q22XQj0rAm1K4A== X-CSE-MsgGUID: 52sPMVgATjm+u4p2NqhtfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="64597923" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by fmviesa009.fm.intel.com with ESMTP; 02 Sep 2024 02:55:10 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: bruce.richardson@intel.com Subject: [PATCH v1 13/30] net/i40e/base: allow reading LED blink setting Date: Mon, 2 Sep 2024 10:54:25 +0100 Message-ID: <07fb02d45a8d6cc8dce145ff6e2b86a3ad468404.1725270827.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dawid Łukwiński Provide an API to allow reading LED blink setting. Signed-off-by: Dawid Łukwiński Signed-off-by: Anatoly Burakov --- drivers/net/i40e/base/i40e_common.c | 29 ++++++++++++++++++++++++++ drivers/net/i40e/base/i40e_prototype.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c index 80500697ed..a43b89aaeb 100644 --- a/drivers/net/i40e/base/i40e_common.c +++ b/drivers/net/i40e/base/i40e_common.c @@ -1568,6 +1568,35 @@ u32 i40e_led_get(struct i40e_hw *hw) return mode; } +/** + * i40e_led_get_blink - return current LED blink setting + * @hw: pointer to the hw struct + * + * The value returned is the LED_BLINK bit as defined in the + * GPIO register definitions (0 = no blink, 1 = do blink). + **/ +bool i40e_led_get_blink(struct i40e_hw *hw) +{ + bool blink = 0; + int i; + + /* as per the documentation GPIO 22-29 are the LED + * GPIO pins named LED0..LED7 + */ + for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { + u32 gpio_val = i40e_led_is_mine(hw, i); + + if (!gpio_val) + continue; + + blink = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK) >> + I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT; + break; + } + + return blink; +} + /** * i40e_led_set - set new on/off mode * @hw: pointer to the hw struct diff --git a/drivers/net/i40e/base/i40e_prototype.h b/drivers/net/i40e/base/i40e_prototype.h index 3fd746a4be..745b9709c5 100644 --- a/drivers/net/i40e/base/i40e_prototype.h +++ b/drivers/net/i40e/base/i40e_prototype.h @@ -69,6 +69,7 @@ const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err); const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err); u32 i40e_led_get(struct i40e_hw *hw); +bool i40e_led_get_blink(struct i40e_hw *hw); void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink); enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, u16 led_addr, u32 mode); -- 2.43.5