From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A3C7454EF; Tue, 25 Jun 2024 13:25:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2791543251; Tue, 25 Jun 2024 13:18:35 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 63215427B8 for ; Tue, 25 Jun 2024 13:17:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314231; x=1750850231; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Uf/1kcVcg/8sFJ4upKoCyI/xCVP4yAkJt+YGCBHMvP0=; b=Hp6QuoSRw9axaGWCiIqhV8Uod5T+UORBj9gbWQtXLlexZBtnuXoJ8aFv WsUuDUoy641S+U8lgl/YLDeJ2DowaYzCHyRNKY8Vyyc5EC0+X4rU5LNFQ j2PicNzOzzRYkS+VKIfWeiw5gC2oNyam6yuGzwjijy6uh51C9ROPsFXTF JeayMlIMa84v/XKNwbNFymWE5inJGu0UYWtlO/DO0+iwzNzsXGgL3Q1wB DreuJ56+mMu/PDaWgf/HMKU2+Z7cxplUsAQrW5yCHs79CGqC4Myzt2hBg 43o+E61YVbxbNwYKp88jhLtJRVdXQLl4QBpSz3Lk8+TgQr3CbXH6c5FDQ Q==; X-CSE-ConnectionGUID: ABcCTYz9TTSygBVwJmuGtw== X-CSE-MsgGUID: ya8ZYzheT0y7iCWLtc+5gw== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080408" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080408" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:17:10 -0700 X-CSE-ConnectionGUID: PwNzBRvnRTmk+s735qnyYQ== X-CSE-MsgGUID: k2Hs2FMhS2+ZZGMhJwqrow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719507" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:17:10 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Sergey Temerkhanov , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 082/129] net/ice/base: rename PHY model designator fields and functions Date: Tue, 25 Jun 2024 12:13:27 +0100 Message-ID: <083ab861e62f2634d8b74d39f287a31c2324cec7.1719313663.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sergey Temerkhanov Rename the PHY model designating fields, functions, etc to make the code more readable and distinguish it from the "PHY type" as described in the documentation. Signed-off-by: Sergey Temerkhanov Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 44 ++++++++++++++++--------------- drivers/net/ice/base/ice_ptp_hw.h | 2 +- drivers/net/ice/base/ice_type.h | 6 ++--- drivers/net/ice/ice_ethdev.c | 6 ++--- 4 files changed, 30 insertions(+), 28 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index ba0880ea4c..dc050011ef 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -846,7 +846,7 @@ static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, /* Certain hardware families share the same register values for the * port register and source timer register. */ - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: case ICE_PHY_E830: return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810; @@ -2274,11 +2274,13 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_err) } /** - * ice_ptp_init_phy_cfg - Get the current TX timestamp err - * mask. Returns the mask of ports where TX timestamps are available - * @hw: pointer to the HW struct + * ice_ptp_init_phy_model - Initialize hw->phy_model based on device type + * @hw: pointer to the HW struct + * + * Determine the PHY configuration for the device, and initialize hw->phy_model + * for use by other functions. */ -int ice_ptp_init_phy_cfg(struct ice_hw *hw) +int ice_ptp_init_phy_model(struct ice_hw *hw) { int err; u32 phy_rev; @@ -2289,14 +2291,14 @@ int ice_ptp_init_phy_cfg(struct ice_hw *hw) return err; if (phy_rev == PHY_REVISION_ETH56G) { - hw->phy_cfg = ICE_PHY_ETH56G; + hw->phy_model = ICE_PHY_ETH56G; return 0; } if (ice_is_e810(hw)) - hw->phy_cfg = ICE_PHY_E810; + hw->phy_model = ICE_PHY_E810; else - hw->phy_cfg = ICE_PHY_E822; + hw->phy_model = ICE_PHY_E822; hw->phy_ports = ICE_NUM_EXTERNAL_PORTS; hw->max_phy_port = ICE_NUM_EXTERNAL_PORTS; @@ -5493,7 +5495,7 @@ void ice_ptp_unlock(struct ice_hw *hw) int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) { - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E822: return ice_ptp_write_port_cmd_e822(hw, port, cmd, lock_sbq); default: @@ -5550,7 +5552,7 @@ static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, u8 port; /* PHY models which can program all ports simultaneously */ - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E830: return ice_ptp_port_cmd_e830(hw, cmd, lock_sbq); case ICE_PHY_E810: @@ -5628,7 +5630,7 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) /* Source timers */ /* For E830 we don't need to use shadow registers, its automatic */ - if (hw->phy_cfg == ICE_PHY_E830) + if (hw->phy_model == ICE_PHY_E830) return ice_ptp_write_direct_phc_time_e830(hw, time); wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time)); @@ -5637,7 +5639,7 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) /* PHY Clks */ /* Fill Rx and Tx ports and send msg to PHY */ - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_ETH56G: err = ice_ptp_prep_phy_time_eth56g(hw, time & 0xFFFFFFFF); break; @@ -5679,14 +5681,14 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; /* For E830 we don't need to use shadow registers, its automatic */ - if (hw->phy_cfg == ICE_PHY_E830) + if (hw->phy_model == ICE_PHY_E830) return ice_ptp_write_direct_incval_e830(hw, incval); /* Shadow Adjust */ wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval)); wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_ETH56G: err = ice_ptp_prep_phy_incval_eth56g(hw, incval); break; @@ -5757,7 +5759,7 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq) wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_ETH56G: err = ice_ptp_prep_phy_adj_eth56g(hw, adj, lock_sbq); break; @@ -5821,7 +5823,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) wr32(hw, GLTSYN_SHTIME_H(tmr_idx), time_hi); /* Prepare PHY port adjustments */ - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_ETH56G: err = ice_ptp_prep_phy_adj_eth56g(hw, adj, true); break; @@ -5839,7 +5841,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) return err; /* Set target time for each PHY port */ - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_ETH56G: err = ice_ptp_prep_phy_adj_target_eth56g(hw, time_lo); break; @@ -5868,7 +5870,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) */ int ice_ptp_clear_phy_offset_ready(struct ice_hw *hw) { - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_ETH56G: return ice_ptp_clear_phy_offset_ready_eth56g(hw); case ICE_PHY_E830: @@ -5897,7 +5899,7 @@ ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) { int err; - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_ETH56G: err = ice_read_phy_tstamp_eth56g(hw, block, idx, tstamp); break; @@ -5931,7 +5933,7 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) { int err; - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_ETH56G: err = ice_clear_phy_tstamp_eth56g(hw, block, idx); break; @@ -5965,7 +5967,7 @@ int ice_ptp_init_phc(struct ice_hw *hw) /* Clear event status indications for auxiliary pins */ (void)rd32(hw, GLTSYN_STAT(src_idx)); - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_ETH56G: err = ice_ptp_init_phc_eth56g(hw); break; diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 266c87baee..42046239a4 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -302,7 +302,7 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass); int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port); int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port); -int ice_ptp_init_phy_cfg(struct ice_hw *hw); +int ice_ptp_init_phy_model(struct ice_hw *hw); #define PFTSYN_SEM_BYTES 4 diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 50e19f1c0c..b55b923055 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1235,8 +1235,8 @@ struct ice_switch_info { ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); }; -/* PHY configuration */ -enum ice_phy_cfg { +/* PHY model */ +enum ice_phy_model { ICE_PHY_E810 = 1, ICE_PHY_E822, ICE_PHY_ETH56G, @@ -1268,7 +1268,7 @@ struct ice_hw { u8 revision_id; u8 pf_id; /* device profile info */ - enum ice_phy_cfg phy_cfg; + enum ice_phy_model phy_model; u8 phy_ports; u8 max_phy_port; u8 logical_pf_id; diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index dec26f8219..9447b44141 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -2513,11 +2513,11 @@ ice_dev_init(struct rte_eth_dev *dev) ice_tm_conf_init(dev); if (ice_is_e810(hw)) - hw->phy_cfg = ICE_PHY_E810; + hw->phy_model = ICE_PHY_E810; else - hw->phy_cfg = ICE_PHY_E822; + hw->phy_model = ICE_PHY_E822; - if (hw->phy_cfg == ICE_PHY_E822) { + if (hw->phy_model == ICE_PHY_E822) { ret = ice_start_phy_timer_e822(hw, hw->pf_id, true); if (ret) PMD_INIT_LOG(ERR, "Failed to start phy timer\n"); -- 2.43.0