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Thu, 15 Mar 2018 09:30:00 +0800 From: "Xu, Rosen" To: "Richardson, Bruce" , =?iso-8859-1?Q?Ga=EBtan_Rivet?= CC: Shreyansh Jain , "dev@dpdk.org" , "Doherty, Declan" , "Zhang, Tianfei" Thread-Topic: [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel FPGA Bus Second Scan, it should be scanned after PCI Bus Thread-Index: AQHTtRNvFIaxRKZ880CIUiXuZapUgKPC8v8ggAAhpMmADXrzkA== Date: Thu, 15 Mar 2018 01:29:59 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D739F1E664@SHSMSX104.ccr.corp.intel.com> References: <1520300638-134954-1-git-send-email-rosen.xu@intel.com> <1520300638-134954-4-git-send-email-rosen.xu@intel.com> <0E78D399C70DA940A335608C6ED296D739F0ED23@SHSMSX104.ccr.corp.intel.com> <20180306104622.3ngsn6syickaphbm@bidouze.vm.6wind.com> <20180306113616.GA7644@bricha3-MOBL3.ger.corp.intel.com> In-Reply-To: <20180306113616.GA7644@bricha3-MOBL3.ger.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZWUzMGNjNTYtNzVkOC00MDFhLWI3NTktNTcyMWY4NDlkNmUwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6IjdPT2k4b29uUmo4UStcL1ZUTkJUUDI0aytaN3pCaVByZDJzaU1XVWJRZ3BVPSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel FPGA Bus Second Scan, it should be scanned after PCI Bus X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Mar 2018 01:30:06 -0000 -----Original Message----- From: Richardson, Bruce=20 Sent: Tuesday, March 06, 2018 19:36 To: Ga?tan Rivet Cc: Xu, Rosen ; Shreyansh Jain = ; dev@dpdk.org; Doherty, Declan ; Zhang, Tianfei = Subject: Re: [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel FPGA Bus= Second Scan, it should be scanned after PCI Bus On Tue, Mar 06, 2018 at 11:46:22AM +0100, Ga=EBtan Rivet wrote: > On Tue, Mar 06, 2018 at 10:42:14AM +0000, Xu, Rosen wrote: > >=20 > >=20 > > -----Original Message----- > > From: Shreyansh Jain [mailto:shreyansh.jain@nxp.com] > > Sent: Tuesday, March 06, 2018 14:20 > > To: Xu, Rosen > > Cc: dev@dpdk.org; Doherty, Declan ; Zhang,=20 > > Tianfei > > Subject: Re: [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel=20 > > FPGA Bus Second Scan, it should be scanned after PCI Bus > >=20 > > On Tue, Mar 6, 2018 at 7:13 AM, Rosen Xu wrote: > > > Signed-off-by: Rosen Xu > > > --- > > > lib/librte_eal/common/eal_common_bus.c | 14 +++++++++++++- > > > 1 file changed, 13 insertions(+), 1 deletion(-) > > > > > > diff --git a/lib/librte_eal/common/eal_common_bus.c > > > b/lib/librte_eal/common/eal_common_bus.c > > > index 3e022d5..74bfa15 100644 > > > --- a/lib/librte_eal/common/eal_common_bus.c > > > +++ b/lib/librte_eal/common/eal_common_bus.c > > > @@ -70,15 +70,27 @@ struct rte_bus_list rte_bus_list =3D > > > rte_bus_scan(void) > > > { > > > int ret; > > > - struct rte_bus *bus =3D NULL; > > > + struct rte_bus *bus =3D NULL, *ifpga_bus =3D NULL; > > > > > > TAILQ_FOREACH(bus, &rte_bus_list, next) { > > > + if (!strcmp(bus->name, "ifpga")) { > > > + ifpga_bus =3D bus; > > > + continue; > > > + } > > > + > > > ret =3D bus->scan(); > > > if (ret) > > > RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\= n", > > > bus->name); > > > } > > > > > > + if (ifpga_bus) { > > > + ret =3D ifpga_bus->scan(); > > > + if (ret) > > > + RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\= n", > > > + ifpga_bus->name); > > > + } > > > + > >=20 > > You are doing this just so that PCI scans are completed *before* ifpga = scans? > > Rosen: yes > > Well, I understand that this certainly is an issue that we can't yet de= fine a priority ordering of bus scans. > >=20 > > But, I think what you are require is a simpler: > >=20 > > In the file ifpga_bus.c: > >=20 > > +RTE_REGISTER_BUS(IFPGA_BUS_NAME, rte_ifpga_bus.bus); <=3D=3D this > > ... > > ... > > #define RTE_REGISTER_BUS(nm, bus) \ > > RTE_INIT_PRIO(businitfn_ ##nm, 110); \ > >=20 > > If you define your own version of RTE_REGISTER_BUS with the priority nu= mber higher, it would be inserted later in the bus list. > > rte_register_bus doesn't do any inherent ordering. > > This would save the changes you are doing in the lib/librte_eal/common/= eal_common_bus.c file. > >=20 > > But I think there has to be a better provision of defining priority of = bus scans - I am sure when new devices come in, there would be possibility = of dependencies as in your case. > > Rosen: is the priority scan of bus is implemented? >=20 > No, there is no priority set for scanning order. > However, the order in which buses are registered, will modify the=20 > order in which scans are done. >=20 > Thus, if you change the priority of your registration, you should be=20 > able to ensure that your scan comes last. >=20 Can we register the bus only when a PCI device match is found at runtime, e= .g. as part of the PCI driver instance initialization? Rosen: yes, in my v1 patch it's called by FPGA PCI Driver(Rawdev) /Bruce