From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 557BD2C12 for ; Sat, 31 Mar 2018 18:25:41 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2018 09:25:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,387,1517904000"; d="scan'208";a="42902033" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga001.fm.intel.com with ESMTP; 31 Mar 2018 09:25:39 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sat, 31 Mar 2018 09:25:39 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sat, 31 Mar 2018 09:25:39 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.226]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.235]) with mapi id 14.03.0319.002; Sun, 1 Apr 2018 00:25:37 +0800 From: "Xu, Rosen" To: "gaetan.rivet@6wind.com" CC: "dev@dpdk.org" , "Doherty, Declan" , "Richardson, Bruce" , "shreyansh.jain@nxp.com" , "Zhang, Tianfei" , "Wu, Hao" Thread-Topic: [PATCH v3 1/6] Add Intel FPGA BUS Command Parse Code Thread-Index: AQHTxphRDwJ90oYOWk2Yxk+243rTeKPqizIQ Date: Sat, 31 Mar 2018 16:25:36 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D739F26797@SHSMSX104.ccr.corp.intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1522229396-17898-1-git-send-email-rosen.xu@intel.com> <1522229396-17898-2-git-send-email-rosen.xu@intel.com> <20180328132603.eqb62ydah2gpdlnz@bidouze.vm.6wind.com> In-Reply-To: <20180328132603.eqb62ydah2gpdlnz@bidouze.vm.6wind.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZWEyZDlmNGYtNDk3YS00MTI5LThjMzctZTVjMmZiMWRjOGQyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6InRrN1hweUszeWxqdWtibEhkMVppSVwvQXNLSUlQcmVLaG1YQ0JFcDhYYnFVPSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 1/6] Add Intel FPGA BUS Command Parse Code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 31 Mar 2018 16:25:41 -0000 > -----Original Message----- > From: Ga=EBtan Rivet [mailto:gaetan.rivet@6wind.com] > Sent: Wednesday, March 28, 2018 21:26 > To: Xu, Rosen > Cc: dev@dpdk.org; Doherty, Declan ; > Richardson, Bruce ; shreyansh.jain@nxp.com; > Zhang, Tianfei ; Wu, Hao > Subject: Re: [PATCH v3 1/6] Add Intel FPGA BUS Command Parse Code >=20 > On Wed, Mar 28, 2018 at 05:29:51PM +0800, Rosen Xu wrote: > > Signed-off-by: Rosen Xu > > --- > > lib/librte_eal/common/eal_common_options.c | 8 +++++++- > > lib/librte_eal/common/eal_options.h | 2 ++ > > 2 files changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/lib/librte_eal/common/eal_common_options.c > > b/lib/librte_eal/common/eal_common_options.c > > index 9f2f8d2..4fe0875 100644 > > --- a/lib/librte_eal/common/eal_common_options.c > > +++ b/lib/librte_eal/common/eal_common_options.c > > @@ -73,6 +73,7 @@ > > {OPT_VDEV, 1, NULL, OPT_VDEV_NUM }, > > {OPT_VFIO_INTR, 1, NULL, OPT_VFIO_INTR_NUM }, > > {OPT_VMWARE_TSC_MAP, 0, NULL, > OPT_VMWARE_TSC_MAP_NUM }, > > + {OPT_IFPGA, 1, NULL, OPT_IFPGA_NUM }, > > {0, 0, NULL, 0 } > > }; > > > > @@ -1160,7 +1161,12 @@ static int xdigit2val(unsigned char c) > > > > core_parsed =3D LCORE_OPT_MAP; > > break; > > - > > + case OPT_IFPGA_NUM: > > + if (eal_option_device_add(RTE_DEVTYPE_VIRTUAL, > > + optarg) < 0) { > > + return -1; > > + } > > + break; >=20 > why do you need to add a new option if you only insert a virtual devargs? >=20 > Why wouldn't --vdev option work instead? and for that matter, I was > expecting you to provide a PCI address. Can you give a command line > showing how you create your device? The devtype is essentially ignored > currently (at option stage, maybe there are still cruft left in PCI bus),= instead > the devargs parsing will detect the bus from the given optarg. >=20 > This part of EAL will change rather soon, I'd prefer not to deal with add= itional > options unless necessary. For PATCH v4, I have removed all the modification from eal library.=20 Create vdev to take IFPGA parameters configuration. The command line for PATCH v4 is(just take 2 AFU for example): testpmd -c 0x3 -n 4 --socket-mem 1024,0 --huge-dir=3D/mnt/huge \ --vdev 'net_ifpga_cfg0,bdf=3D5e:00.0,port=3D0,afu_bts=3D./xxx.gbs' \ --vdev 'net_ifpga_cfg1,bdf=3Dbe:00.0,port=3D0,afu_bts=3D./xxx.gbs' -- -i -= -no-numa Note: the parameter of "port" is used by OPAE for download bitstream. > > /* don't know what to do, leave this to caller */ > > default: > > return 1; > > diff --git a/lib/librte_eal/common/eal_options.h > > b/lib/librte_eal/common/eal_options.h > > index e86c711..bdbb2c4 100644 > > --- a/lib/librte_eal/common/eal_options.h > > +++ b/lib/librte_eal/common/eal_options.h > > @@ -55,6 +55,8 @@ enum { > > OPT_VFIO_INTR_NUM, > > #define OPT_VMWARE_TSC_MAP "vmware-tsc-map" > > OPT_VMWARE_TSC_MAP_NUM, > > +#define OPT_IFPGA "ifpga" > > + OPT_IFPGA_NUM, > > OPT_LONG_MAX_NUM > > }; > > > > -- > > 1.8.3.1 > > >=20 > -- > Ga=EBtan Rivet > 6WIND