From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <rosen.xu@intel.com> Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id AD38C1B8DE for <dev@dpdk.org>; Wed, 4 Apr 2018 04:01:18 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Apr 2018 19:01:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,404,1517904000"; d="scan'208";a="29907960" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga008.fm.intel.com with ESMTP; 03 Apr 2018 19:01:17 -0700 Received: from fmsmsx125.amr.corp.intel.com (10.18.125.40) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 3 Apr 2018 19:01:17 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX125.amr.corp.intel.com (10.18.125.40) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 3 Apr 2018 19:01:17 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.43]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.241]) with mapi id 14.03.0319.002; Wed, 4 Apr 2018 10:01:14 +0800 From: "Xu, Rosen" <rosen.xu@intel.com> To: "gaetan.rivet@6wind.com" <gaetan.rivet@6wind.com> CC: "dev@dpdk.org" <dev@dpdk.org>, "Doherty, Declan" <declan.doherty@intel.com>, "Richardson, Bruce" <bruce.richardson@intel.com>, "shreyansh.jain@nxp.com" <shreyansh.jain@nxp.com>, "Zhang, Tianfei" <tianfei.zhang@intel.com>, "Wu, Hao" <hao.wu@intel.com> Thread-Topic: [PATCH v3 2/6] config/common_base: Add Intel FPGA Build Configuration Macro Thread-Index: AQHTxpiDBxJb3kXWjU67yeC+gNs2pqPv4+zw Date: Wed, 4 Apr 2018 02:01:14 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D739F33DF1@SHSMSX104.ccr.corp.intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1522229396-17898-1-git-send-email-rosen.xu@intel.com> <1522229396-17898-3-git-send-email-rosen.xu@intel.com> <20180328132726.ixwzcwaejetjyltw@bidouze.vm.6wind.com> In-Reply-To: <20180328132726.ixwzcwaejetjyltw@bidouze.vm.6wind.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNDVjMWNlZDItNmY1Zi00MzM2LTk1OGUtYWVlMjMwNGZhODY2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6Ild6a3A2UHRqNHREa1lIczM2SjExOXEwOHBnVEptK2QzT1M4SEpFU24xb0E9In0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 2/6] config/common_base: Add Intel FPGA Build Configuration Macro X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://dpdk.org/ml/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://dpdk.org/ml/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://dpdk.org/ml/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Wed, 04 Apr 2018 02:01:19 -0000 Hi Gaetan, I have squash this patch with their relevant counterparts. For PATCH v4 and later version CONFIG_RTE_LIBRTE_IFPGA_BUS is squashed with= ifpga_bus driver, And CONFIG_RTE_LIBRTE_IFPGA_RAWDEV is squashed with ifpga_rawdev driver. Is it ok? > -----Original Message----- > From: Ga=EBtan Rivet [mailto:gaetan.rivet@6wind.com] > Sent: Wednesday, March 28, 2018 21:27 > To: Xu, Rosen <rosen.xu@intel.com> > Cc: dev@dpdk.org; Doherty, Declan <declan.doherty@intel.com>; > Richardson, Bruce <bruce.richardson@intel.com>; shreyansh.jain@nxp.com; > Zhang, Tianfei <tianfei.zhang@intel.com>; Wu, Hao <hao.wu@intel.com> > Subject: Re: [PATCH v3 2/6] config/common_base: Add Intel FPGA Build > Configuration Macro >=20 > On Wed, Mar 28, 2018 at 05:29:52PM +0800, Rosen Xu wrote: > > Signed-off-by: Rosen Xu <rosen.xu@intel.com> > > --- > > config/common_base | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/config/common_base b/config/common_base index > > ad03cf4..08b7cce 100644 > > --- a/config/common_base > > +++ b/config/common_base > > @@ -134,6 +134,12 @@ CONFIG_RTE_LIBRTE_PCI_BUS=3Dy > > CONFIG_RTE_LIBRTE_VDEV_BUS=3Dy > > > > # > > +# Compile the Intel FPGA bus > > +# > > +CONFIG_RTE_LIBRTE_IFPGA_BUS=3Dy > > +CONFIG_RTE_LIBRTE_IFPGA_RAWDEV=3Dy > > + > > +# >=20 > Please squash this patch with their relevant counterparts. > As it is, this won't trigger an error but the patch is meaningless. >=20 > > # Compile ARK PMD > > # > > CONFIG_RTE_LIBRTE_ARK_PMD=3Dy > > -- > > 1.8.3.1 > > >=20 > -- > Ga=EBtan Rivet > 6WIND