From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 8E383A045E for ; Fri, 31 May 2019 08:17:28 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9317D493D; Fri, 31 May 2019 08:17:26 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 5E0A62C55; Fri, 31 May 2019 08:17:24 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 May 2019 23:17:23 -0700 X-ExtLoop1: 1 Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga004.fm.intel.com with ESMTP; 30 May 2019 23:17:23 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 30 May 2019 23:17:22 -0700 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 30 May 2019 23:17:22 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.137]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.188]) with mapi id 14.03.0415.000; Fri, 31 May 2019 14:17:10 +0800 From: "Xu, Rosen" To: "Wei, Dan" , "dev@dpdk.org" CC: "Yigit, Ferruh" , "stable@dpdk.org" Thread-Topic: [DPDK v2] net/ipn3ke: modifications on AFU configurations Thread-Index: AQHVFpKggPhmNelLiEGWrOMJ1JXeWKaEwm7g Date: Fri, 31 May 2019 06:17:09 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D73A7A536E@SHSMSX104.ccr.corp.intel.com> References: <1559228335-35214-1-git-send-email-dan.wei@intel.com> In-Reply-To: <1559228335-35214-1-git-send-email-dan.wei@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODI4ZTY1YTAtZjVmZC00ZGQyLTlkNjItNWIxYjY1N2Y1MDVlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoia3A3ODNtYktqXC9mWGE5dVZjM1JcL3pWY2VqclwvU1hrVTM0SDI4T25oMHZIUU5za2ZBRjltYVd3U1dJblpQTzAweSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [DPDK v2] net/ipn3ke: modifications on AFU configurations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: Wei, Dan > Sent: Thursday, May 30, 2019 22:59 > To: dev@dpdk.org > Cc: Yigit, Ferruh ; Wei, Dan ; > Xu, Rosen ; stable@dpdk.org > Subject: [DPDK v2] net/ipn3ke: modifications on AFU configurations >=20 > Modify AFU configurations for new Blue Bitstream of A10 on N3000 card: Blue Bitstream is new term, pls explain it or take modification. > - AFU register access: RTL changes the UPL base address and the read/writ= e > commands of register indirect access. What means UPL? Could you descript it in more common language? > - Add delays to wait for the HW reset completion. Does HW same means with RTL? > - Refine log for debug: print UPL_version not only for vBNG bit stream, b= ut > also for other bit streams >=20 > Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver") > Cc: rosen.xu@intel.com > Cc: stable@dpdk.org >=20 > Signed-off-by: Dan Wei > --- > drivers/net/ipn3ke/ipn3ke_ethdev.c | 14 ++++++++++++-- > drivers/net/ipn3ke/ipn3ke_ethdev.h | 9 +++++---- > drivers/net/ipn3ke/ipn3ke_flow.c | 1 + > 3 files changed, 18 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c > b/drivers/net/ipn3ke/ipn3ke_ethdev.c > index 9079b57..84eb0e9 100644 > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c > @@ -223,15 +223,25 @@ > "LineSideMACType", &mac_type); > hw->retimer.mac_type =3D (int)mac_type; >=20 > + /* After power on, wait until init done */ > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) !=3D 0x3) > + ; > + > + IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", > IPN3KE_READ_REG(hw, 0)); > + > if (afu_dev->id.uuid.uuid_low =3D=3D IPN3KE_UUID_VBNG_LOW && > afu_dev->id.uuid.uuid_high =3D=3D IPN3KE_UUID_VBNG_HIGH) { > ipn3ke_hw_cap_init(hw); > - IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", > - IPN3KE_READ_REG(hw, 0)); Why did you remove Debug code? > /* Reset FPGA IP */ > IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1); > + rte_delay_us(10); > IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0); > + > + /* After reset, wait until init done */ > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) !=3D 0x3) > + ; > + rte_delay_us(10); > } >=20 > if (hw->retimer.mac_type =3D=3D > IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) { diff --git > a/drivers/net/ipn3ke/ipn3ke_ethdev.h > b/drivers/net/ipn3ke/ipn3ke_ethdev.h > index bfda9d5..686c12f 100644 > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h > @@ -344,7 +344,6 @@ static inline uint32_t ipn3ke_read_addr(volatile void > *addr) >=20 > #define WCMD 0x8000000000000000 > #define RCMD 0x4000000000000000 > -#define UPL_BASE 0x10000 > static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw, > uint32_t addr) > { > @@ -355,13 +354,13 @@ static inline uint32_t _ipn3ke_indrct_read(struct > ipn3ke_hw *hw, >=20 > word_offset =3D (addr & 0x1FFFFFF) >> 2; > indirect_value =3D RCMD | word_offset << 32; > - indirect_addrs =3D hw->hw_addr + (uint32_t)(UPL_BASE | 0x10); > + indirect_addrs =3D hw->hw_addr + (uint32_t)(0x30); >=20 > rte_delay_us(10); >=20 > rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); >=20 > - indirect_addrs =3D hw->hw_addr + (uint32_t)(UPL_BASE | 0x18); > + indirect_addrs =3D hw->hw_addr + (uint32_t)(0x38); > while ((read_data >> 32) !=3D 1) > read_data =3D rte_read64(indirect_addrs); >=20 > @@ -377,7 +376,7 @@ static inline void _ipn3ke_indrct_write(struct > ipn3ke_hw *hw, >=20 > word_offset =3D (addr & 0x1FFFFFF) >> 2; > indirect_value =3D WCMD | word_offset << 32 | value; > - indirect_addrs =3D hw->hw_addr + (uint32_t)(UPL_BASE | 0x10); > + indirect_addrs =3D hw->hw_addr + (uint32_t)(0x30); >=20 > rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); > rte_delay_us(10); > @@ -411,6 +410,7 @@ static inline void _ipn3ke_indrct_write(struct > ipn3ke_hw *hw, > (&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm)) >=20 > /* Byte address of IPN3KE internal module */ > +#define IPN3KE_INIT_DONE (0x204) > #define IPN3KE_TM_VERSION (IPN3KE_QM_OFFSET + 0x0000= ) > #define IPN3KE_TM_SCRATCH (IPN3KE_QM_OFFSET + 0x0004= ) > #define IPN3KE_TM_STATUS (IPN3KE_QM_OFFSET + 0x0008= ) > @@ -500,6 +500,7 @@ static inline void _ipn3ke_indrct_write(struct > ipn3ke_hw *hw, > #define IPN3KE_CLF_RX_TEST (IPN3KE_CLASSIFY_OFFSET + = 0x0400) >=20 > #define IPN3KE_CLF_EM_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x40000 > + 0x0000) > +#define IPN3KE_CLF_EM_SCRATCH (IPN3KE_CLASSIFY_OFFSET + 0x40000 > + 0x0004) > #define IPN3KE_CLF_EM_NUM (IPN3KE_CLASSIFY_OFFSET + 0x40000 + > 0x0008) > #define IPN3KE_CLF_EM_KEY_WDTH (IPN3KE_CLASSIFY_OFFSET + > 0x40000 + 0x000C) > #define IPN3KE_CLF_EM_RES_WDTH (IPN3KE_CLASSIFY_OFFSET + > 0x40000 + 0x0010) > diff --git a/drivers/net/ipn3ke/ipn3ke_flow.c > b/drivers/net/ipn3ke/ipn3ke_flow.c > index e5937df..ff9f064 100644 > --- a/drivers/net/ipn3ke/ipn3ke_flow.c > +++ b/drivers/net/ipn3ke/ipn3ke_flow.c > @@ -1360,6 +1360,7 @@ int ipn3ke_flow_init(void *dev) > IPN3KE_CLF_EM_NUM, > 0, > 0xFFFFFFFF); > + IPN3KE_AFU_PMD_DEBUG("IPN3KE_CLF_EN_NUM: %x\n", hw- > >flow_max_entries); > hw->flow_num_entries =3D 0; >=20 > return 0; > -- > 1.8.3.1