From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 00A82A0487 for ; Mon, 1 Jul 2019 12:31:59 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5C72D1B203; Mon, 1 Jul 2019 12:31:58 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 4183D235; Mon, 1 Jul 2019 12:31:56 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Jul 2019 03:31:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,439,1557212400"; d="scan'208";a="154039595" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga007.jf.intel.com with ESMTP; 01 Jul 2019 03:31:55 -0700 Received: from fmsmsx151.amr.corp.intel.com (10.18.125.4) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 1 Jul 2019 03:31:54 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX151.amr.corp.intel.com (10.18.125.4) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 1 Jul 2019 03:31:54 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.110]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.109]) with mapi id 14.03.0439.000; Mon, 1 Jul 2019 18:31:52 +0800 From: "Xu, Rosen" To: "Zhang, Tianfei" , "dev@dpdk.org" , "Yigit, Ferruh" CC: "stable@dpdk.org" Thread-Topic: [PATCH v4 5/5] raw/ifpga_rawdev/base: fix retimer link status issue Thread-Index: AQHVJ8wL4iHvr8hk7Em5CcvigX3o7aa1oMBg Date: Mon, 1 Jul 2019 10:31:52 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D73A85CA66@SHSMSX104.ccr.corp.intel.com> References: <20190621084017.6763-1-tianfei.zhang@intel.com> <20190621084017.6763-5-tianfei.zhang@intel.com> In-Reply-To: <20190621084017.6763-5-tianfei.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjEyMzAyMDMtZmM3Ny00ZTE5LWFlZDctYjFjNDdkYjM2Yzg3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZjlpUEE3bjlYWVlkYWtuZGRUdGI1c1E4eTZJXC8yd0JEdktwdkdHaU5qcFJaNzBMWUhYT09IMlRyaGtuVkl4MGUifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 5/5] raw/ifpga_rawdev/base: fix retimer link status issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Zhang, Tianfei > Sent: Friday, June 21, 2019 16:40 > To: dev@dpdk.org; Yigit, Ferruh > Cc: Xu, Rosen ; stable@dpdk.org; Zhang, Tianfei > > Subject: [PATCH v4 5/5] raw/ifpga_rawdev/base: fix retimer link status is= sue >=20 > Fix the readout retimer link status incorrectly when we remove the linux > intel-fpga-driver and run the DPDK application. > The linux driver will stop the retimer when remove the kernel modules. >=20 > Fixes: 8a256bef ("raw/ifpga/base: add eth group driver") > Cc: stable@dpdk.org >=20 > Reported-by: Sampath Amrutha > Signed-off-by: Tianfei zhang > --- > .../raw/ifpga_rawdev/base/opae_eth_group.c | 172 ++++++++++++++++++ > .../raw/ifpga_rawdev/base/opae_eth_group.h | 6 + > .../raw/ifpga_rawdev/base/opae_intel_max10.c | 7 - > 3 files changed, 178 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/raw/ifpga_rawdev/base/opae_eth_group.c > b/drivers/raw/ifpga_rawdev/base/opae_eth_group.c > index 8db6693b1..d189dd578 100644 > --- a/drivers/raw/ifpga_rawdev/base/opae_eth_group.c > +++ b/drivers/raw/ifpga_rawdev/base/opae_eth_group.c > @@ -113,6 +113,171 @@ int eth_group_read_reg(struct eth_group_device > *dev, > return 0; > } >=20 > +static int eth_group_reset_mac(struct eth_group_device *dev, u8 index, > + bool enable) > +{ > + u32 val; > + int ret; > + > + /* > + * only support 25G & 40G mac reset for now. It uses internal reset. > + * as PHY and MAC are integrated together, below action will trigger > + * PHY reset too. > + */ > + if (dev->speed !=3D 25 && dev->speed !=3D 40) > + return 0; > + > + ret =3D eth_group_read_reg(dev, ETH_GROUP_MAC, index, > MAC_CONFIG, > + &val); > + if (ret) { > + dev_err(dev, "fail to read PHY_CONFIG: %d\n", ret); > + return ret; > + } > + > + /* skip if mac is in expected state already */ > + if ((((val & MAC_RESET_MASK) =3D=3D MAC_RESET_MASK) && enable) || > + (((val & MAC_RESET_MASK) =3D=3D 0) && !enable)) > + return 0; > + > + if (enable) > + val |=3D MAC_RESET_MASK; > + else > + val &=3D ~MAC_RESET_MASK; > + > + ret =3D eth_group_write_reg(dev, ETH_GROUP_MAC, index, > MAC_CONFIG, > + val); > + if (ret) > + dev_err(dev, "fail to write PHY_CONFIG: %d\n", ret); > + > + return ret; > +} > + > +static void eth_group_mac_uinit(struct eth_group_device *dev) { > + u8 i; > + > + for (i =3D 0; i < dev->mac_num; i++) { > + if (eth_group_reset_mac(dev, i, true)) > + dev_err(dev, "fail to disable mac %d\n", i); > + } > +} > + > +static int eth_group_mac_init(struct eth_group_device *dev) { > + int ret; > + u8 i; > + > + for (i =3D 0; i < dev->mac_num; i++) { > + ret =3D eth_group_reset_mac(dev, i, false); > + if (ret) { > + dev_err(dev, "fail to enable mac %d\n", i); > + goto exit; > + } > + } > + > + return 0; > + > +exit: > + while (i--) > + eth_group_reset_mac(dev, i, true); > + > + return ret; > +} > + > +static int eth_group_reset_phy(struct eth_group_device *dev, u8 index, > + bool enable) > +{ > + u32 val; > + int ret; > + > + /* only support 10G PHY reset for now. It uses external reset. */ > + if (dev->speed !=3D 10) > + return 0; > + > + ret =3D eth_group_read_reg(dev, ETH_GROUP_PHY, index, > + ADD_PHY_CTRL, &val); > + if (ret) { > + dev_err(dev, "fail to read ADD_PHY_CTRL reg: %d\n", ret); > + return ret; > + } > + > + /* return if PHY is already in expected state */ > + if ((val & PHY_RESET && enable) || (!(val & PHY_RESET) && !enable)) > + return 0; > + > + if (enable) > + val |=3D PHY_RESET; > + else > + val &=3D ~PHY_RESET; > + > + ret =3D eth_group_write_reg(dev, ETH_GROUP_PHY, index, > + ADD_PHY_CTRL, val); > + if (ret) > + dev_err(dev, "fail to write ADD_PHY_CTRL reg: %d\n", ret); > + > + return ret; > +} > + > +static int eth_group_phy_init(struct eth_group_device *dev) { > + int ret; > + int i; > + > + for (i =3D 0; i < dev->phy_num; i++) { > + ret =3D eth_group_reset_phy(dev, i, false); > + if (ret) { > + dev_err(dev, "fail to enable phy %d\n", i); > + goto exit; > + } > + } > + > + return 0; > +exit: > + while (i--) > + eth_group_reset_phy(dev, i, true); > + > + return ret; > +} > + > +static void eth_group_phy_uinit(struct eth_group_device *dev) { > + int i; > + > + for (i =3D 0; i < dev->phy_num; i++) { > + if (eth_group_reset_phy(dev, i, true)) > + dev_err(dev, "fail to disable phy %d\n", i); > + } > +} > + > +static int eth_group_hw_init(struct eth_group_device *dev) { > + int ret; > + > + ret =3D eth_group_phy_init(dev); > + if (ret) { > + dev_err(dev, "fail to init eth group phys\n"); > + return ret; > + } > + > + ret =3D eth_group_mac_init(dev); > + if (ret) { > + dev_err(priv->dev, "fail to init eth group macs\n"); > + goto phy_exit; > + } > + > + return 0; > + > +phy_exit: > + eth_group_phy_uinit(dev); > + return ret; > +} > + > +static void eth_group_hw_uinit(struct eth_group_device *dev) { > + eth_group_mac_uinit(dev); > + eth_group_phy_uinit(dev); > +} > + > struct eth_group_device *eth_group_probe(void *base) { > struct eth_group_device *dev; > @@ -130,6 +295,11 @@ struct eth_group_device *eth_group_probe(void > *base) >=20 > dev->status =3D ETH_GROUP_DEV_ATTACHED; >=20 > + if (eth_group_hw_init(dev)) { > + dev_err(dev, "eth group hw init fail\n"); > + return NULL; > + } > + > dev_info(dev, "eth group device %d probe done: > phy_num=3Dmac_num:%d, speed=3D%d\n", > dev->group_id, dev->phy_num, dev->speed); >=20 > @@ -138,6 +308,8 @@ struct eth_group_device *eth_group_probe(void > *base) >=20 > void eth_group_release(struct eth_group_device *dev) { > + eth_group_hw_uinit(dev); > + > if (dev) { > dev->status =3D ETH_GROUP_DEV_NOUSED; > opae_free(dev); > diff --git a/drivers/raw/ifpga_rawdev/base/opae_eth_group.h > b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h > index a66d77e27..4868bd0e1 100644 > --- a/drivers/raw/ifpga_rawdev/base/opae_eth_group.h > +++ b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h > @@ -44,6 +44,12 @@ > #define STAT_DATA_VAL BIT_ULL(32) > #define STAT_RD_DATA GENMASK_ULL(31, 0) >=20 > +/* Additional Feature Register */ > +#define ADD_PHY_CTRL 0x0 > +#define PHY_RESET BIT(0) > +#define MAC_CONFIG 0x310 > +#define MAC_RESET_MASK GENMASK(2, 0) > + > struct opae_eth_group_info { > u8 group_id; > u8 speed; > diff --git a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c > b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c > index 3ff6575d7..9ed10e282 100644 > --- a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c > +++ b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c > @@ -57,13 +57,6 @@ intel_max10_device_probe(struct altera_spi_device > *spi, > } > dev_info(dev, "FPGA loaded from %s Image\n", val ? "User" : > "Factory"); >=20 > - /* set PKVL Polling manually in BBS */ > - ret =3D max10_reg_write(PKVL_POLLING_CTRL, 0x3); > - if (ret !=3D 0) { > - dev_err(dev, "%s set PKVL polling fail\n", __func__); > - goto spi_tran_fail; > - } > - > return dev; >=20 > spi_tran_fail: > -- > 2.17.1 Acked-by: Rosen Xu