From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AAECFA0487 for ; Tue, 2 Jul 2019 12:00:47 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8B30F1B993; Tue, 2 Jul 2019 12:00:47 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 2BE701B946 for ; Tue, 2 Jul 2019 12:00:46 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Jul 2019 03:00:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,442,1557212400"; d="scan'208";a="166136310" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga003.jf.intel.com with ESMTP; 02 Jul 2019 03:00:45 -0700 Received: from fmsmsx163.amr.corp.intel.com (10.18.125.72) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 2 Jul 2019 03:00:44 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx163.amr.corp.intel.com (10.18.125.72) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 2 Jul 2019 03:00:44 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.110]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.22]) with mapi id 14.03.0439.000; Tue, 2 Jul 2019 18:00:42 +0800 From: "Xu, Rosen" To: "Pei, Andy" , "dev@dpdk.org" , "Yigit, Ferruh" , "Zhang, Tianfei" Thread-Topic: [PATCH v5 3/4] net/ipn3ke: clear statistics when init and start dev Thread-Index: AQHVL/n2z50vvitC50izjdDXt2JtFKa3GfoQ Date: Tue, 2 Jul 2019 10:00:42 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D73A863A36@SHSMSX104.ccr.corp.intel.com> References: <1561449612-26372-4-git-send-email-andy.pei@intel.com> <1561977388-51692-1-git-send-email-andy.pei@intel.com> <1561977388-51692-3-git-send-email-andy.pei@intel.com> In-Reply-To: <1561977388-51692-3-git-send-email-andy.pei@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjMyY2I4MWEtZGZkYi00ZjY0LTg3ZWYtNDJhMmIxZGI5ZmRlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMVdEbGpoZHVsY0NnQ2lla1VnV2hoeFBUOFZ5QUc2MFRBWklWdkoxXC9peEtCdlVvOFwveDF3RStoOFRmc2FaMDh2In0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v5 3/4] net/ipn3ke: clear statistics when init and start dev X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Pei, Andy > Sent: Monday, July 01, 2019 18:36 > To: dev@dpdk.org > Cc: Pei, Andy ; Xu, Rosen > Subject: [PATCH v5 3/4] net/ipn3ke: clear statistics when init and start = dev >=20 > clear line side and NIC side statistics registers when HW init and uinit,= and > when dev start. >=20 > Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver") > Cc: rosen.xu@intel.com >=20 > Signed-off-by: Andy Pei > --- > drivers/net/ipn3ke/ipn3ke_ethdev.c | 59 > ++++++++++++++++++++++++++++----- > drivers/net/ipn3ke/ipn3ke_representor.c | 27 ++++++++++++--- > 2 files changed, 74 insertions(+), 12 deletions(-) >=20 > diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c > b/drivers/net/ipn3ke/ipn3ke_ethdev.c > index 8d3084d..27ebfb5 100644 > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c > @@ -244,11 +244,33 @@ > /* Enable the RX path */ > ipn3ke_xmac_rx_enable(hw, i, 1); >=20 > - /* Clear all TX statistics counters */ > - ipn3ke_xmac_tx_clr_stcs(hw, i, 1); > + /* Clear NIC side TX statistics counters */ > + ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1); >=20 > - /* Clear all RX statistics counters */ > - ipn3ke_xmac_rx_clr_stcs(hw, i, 1); > + /* Clear NIC side RX statistics counters */ > + ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1); > + > + /* Clear line side TX statistics counters */ > + ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0); > + > + /* Clear line RX statistics counters */ > + ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0); > + } > + } else if (hw->retimer.mac_type =3D=3D > + IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) > { > + /* Enable inter connect channel */ > + for (i =3D 0; i < hw->port_num; i++) { > + /* Clear NIC side TX statistics counters */ > + ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1); > + > + /* Clear NIC side RX statistics counters */ > + ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1); > + > + /* Clear line side TX statistics counters */ > + ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0); > + > + /* Clear line side RX statistics counters */ > + ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0); > } > } >=20 > @@ -291,11 +313,32 @@ > /* Disable the RX path */ > ipn3ke_xmac_rx_disable(hw, i, 1); >=20 > - /* Clear all TX statistics counters */ > - ipn3ke_xmac_tx_clr_stcs(hw, i, 1); > + /* Clear NIC side TX statistics counters */ > + ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1); > + > + /* Clear NIC side RX statistics counters */ > + ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1); > + > + /* Clear line side TX statistics counters */ > + ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0); > + > + /* Clear line side RX statistics counters */ > + ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0); > + } > + } else if (hw->retimer.mac_type =3D=3D > + IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) > { > + for (i =3D 0; i < hw->port_num; i++) { > + /* Clear NIC side TX statistics counters */ > + ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1); > + > + /* Clear NIC side RX statistics counters */ > + ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1); > + > + /* Clear line side TX statistics counters */ > + ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0); >=20 > - /* Clear all RX statistics counters */ > - ipn3ke_xmac_rx_clr_stcs(hw, i, 1); > + /* Clear line side RX statistics counters */ > + ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0); > } > } > } > diff --git a/drivers/net/ipn3ke/ipn3ke_representor.c > b/drivers/net/ipn3ke/ipn3ke_representor.c > index 01ad92e..4456d9d 100644 > --- a/drivers/net/ipn3ke/ipn3ke_representor.c > +++ b/drivers/net/ipn3ke/ipn3ke_representor.c > @@ -159,11 +159,30 @@ > /* Enable the RX path */ > ipn3ke_xmac_rx_enable(hw, rpst->port_id, 0); >=20 > - /* Clear all TX statistics counters */ > - ipn3ke_xmac_tx_clr_stcs(hw, rpst->port_id, 0); > + /* Clear line side TX statistics counters */ > + ipn3ke_xmac_tx_clr_10G_stcs(hw, rpst->port_id, 0); >=20 > - /* Clear all RX statistics counters */ > - ipn3ke_xmac_rx_clr_stcs(hw, rpst->port_id, 0); > + /* Clear line side RX statistics counters */ > + ipn3ke_xmac_rx_clr_10G_stcs(hw, rpst->port_id, 0); > + > + /* Clear NIC side TX statistics counters */ > + ipn3ke_xmac_tx_clr_10G_stcs(hw, rpst->port_id, 1); > + > + /* Clear NIC side RX statistics counters */ > + ipn3ke_xmac_rx_clr_10G_stcs(hw, rpst->port_id, 1); > + } else if (hw->retimer.mac_type =3D=3D > + > IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { > + /* Clear line side TX statistics counters */ > + ipn3ke_xmac_tx_clr_25G_stcs(hw, rpst->port_id, 0); > + > + /* Clear line side RX statistics counters */ > + ipn3ke_xmac_rx_clr_25G_stcs(hw, rpst->port_id, 0); > + > + /* Clear NIC side TX statistics counters */ > + ipn3ke_xmac_tx_clr_25G_stcs(hw, rpst->port_id, 1); > + > + /* Clear NIC side RX statistics counters */ > + ipn3ke_xmac_rx_clr_25G_stcs(hw, rpst->port_id, 1); > } >=20 > ipn3ke_rpst_link_update(dev, 0); > -- > 1.8.3.1 Acked-by: Rosen Xu