From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 35082A10DA for ; Fri, 2 Aug 2019 09:05:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4B9951C22D; Fri, 2 Aug 2019 09:05:01 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id E5B281C20C for ; Fri, 2 Aug 2019 09:04:58 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Aug 2019 00:04:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,337,1559545200"; d="scan'208";a="324492562" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga004.jf.intel.com with ESMTP; 02 Aug 2019 00:04:57 -0700 Received: from fmsmsx601.amr.corp.intel.com (10.18.126.81) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 2 Aug 2019 00:04:57 -0700 Received: from fmsmsx601.amr.corp.intel.com (10.18.126.81) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 2 Aug 2019 00:04:56 -0700 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Fri, 2 Aug 2019 00:04:56 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.112]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.204]) with mapi id 14.03.0439.000; Fri, 2 Aug 2019 15:04:54 +0800 From: "Xu, Rosen" To: Jerin Jacob Kollanukkaran , "dev@dpdk.org" CC: "Yigit, Ferruh" , "Zhang, Tianfei" , "Pei, Andy" , "Lomartire, David" , "Zhang, Qi Z" , "Ye, Xiaolong" Thread-Topic: [dpdk-dev] [PATCH v2 00/12] Add PCIe AER disable and IRQ support for ipn3ke Thread-Index: AQHVSNAlRtWpLrIKnEqX/YRzyoZfRqbnO6kwgAAwknA= Date: Fri, 2 Aug 2019 07:04:53 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D73A913C92@SHSMSX104.ccr.corp.intel.com> References: <1564556752-19257-2-git-send-email-rosen.xu@intel.com> <1564708727-164887-1-git-send-email-rosen.xu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiN2Y2OGY0NGUtYTk1Yy00ZjcxLWFhNDEtY2IwZTBjOTc5MzZjIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiNm9KajZyN2hmK2tPdTduMys4amdnc3IzT2lQcm1nWFwvajVlc01QdldlZHF1MkpZQ3Frcjc0MDR1SjVNeUd1Z3IifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 00/12] Add PCIe AER disable and IRQ support for ipn3ke X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: Jerin Jacob Kollanukkaran [mailto:jerinj@marvell.com] > Sent: Friday, August 02, 2019 12:15 > To: Xu, Rosen ; dev@dpdk.org > Cc: Yigit, Ferruh ; Zhang, Tianfei > ; Pei, Andy ; Lomartire, > David ; Zhang, Qi Z ; Ye= , > Xiaolong > Subject: RE: [dpdk-dev] [PATCH v2 00/12] Add PCIe AER disable and IRQ > support for ipn3ke >=20 > > -----Original Message----- > > From: dev On Behalf Of Rosen Xu > > Sent: Friday, August 2, 2019 6:49 AM > > To: dev@dpdk.org > > Cc: ferruh.yigit@intel.com; tianfei.zhang@intel.com; > > rosen.xu@intel.com; andy.pei@intel.com; david.lomartire@intel.com; > > qi.z.zhang@intel.com; xiaolong.ye@intel.com > > Subject: [dpdk-dev] [PATCH v2 00/12] Add PCIe AER disable and IRQ > > support for ipn3ke > > > > This patch set adds PCIe AER disable and IRQ support for ipn3ke. > > Disable PCIe AER is very useful when FPGA reload. IRQ is used very > > widely in interrupt process. >=20 > Shouldn't it better to have common code in PCI subsystem to disable PCIe > AER etc, So that other drivers can be used in future. That's a good proposal. But there's something special in IPN3KE. In IPN3KE, one Intel A10 FPGA and two I40e are connected to CPU with PCIe switch chip, there are some errors when PCIe switch chip bonding to VFIO, in our design, we access PCIe configure space with pread/pwrite. For AER disable, we need access PCIe switch chip configuration space. > > > > For ipn3ke is connect to CPU with PCIe switch, driver needs to scan > > all PCIe >=20 > Do we need a special PCIe switch for this? Or Generic PCIe switch would d= o? It's hardware specific. =20 > > devices of ipn3ke, it also can get all i40e of card, so ipn3ke driver > > doesn't need to take some configuration of i40e. >=20 > Is communication between i40e and ipn3ke proprietary scheme? Yes. > Who is the PCIe bus master here? Ipn3ke or i40e? >From DPDK point of view, there are 3 PCIe devices in DPDK one Intel A10 FP= GA and two I40e. No master. >=20 >=20