From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E6CAA0588; Thu, 16 Apr 2020 03:09:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 32CEB1D93B; Thu, 16 Apr 2020 03:09:27 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 8B6251D935 for ; Thu, 16 Apr 2020 03:09:24 +0200 (CEST) IronPort-SDR: yNhab1qsbfJnBRgacAmZaP2p1NG2cpj/K9sAtwOzBbGOJ1x/RK6mmmZoMY63j6mTxS+r/cSgKV OdBwb/WHTCPg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2020 18:09:23 -0700 IronPort-SDR: L0dqMwoarKCju9ZdRxRj4X4nZyXH9RI7HElC+6WdpyIqeYFopf7rR4UgUH81kTrCn8lPRvk63b b6WyjSvxJVNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,388,1580803200"; d="scan'208";a="277809401" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga004.fm.intel.com with ESMTP; 15 Apr 2020 18:09:22 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 15 Apr 2020 18:09:22 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 15 Apr 2020 18:09:21 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.225]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.209]) with mapi id 14.03.0439.000; Thu, 16 Apr 2020 09:09:18 +0800 From: "Xu, Rosen" To: "Chautru, Nicolas" , "dev@dpdk.org" CC: "Richardson, Bruce" , "O'Hare, Cathal" , "akhil.goyal@nxp.com" , "Yigit, Ferruh" , "O'Driscoll, Tim" , "Mcnamara, John" Thread-Topic: [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add queue configuration Thread-Index: AQHWBicJq64l3B4afUSIi+X+hr/JtKhzUQAggAQAcACAAntZoIAAHDSAgAEhGFA= Date: Thu, 16 Apr 2020 01:09:17 +0000 Message-ID: <0E78D399C70DA940A335608C6ED296D73AF191EA@SHSMSX104.ccr.corp.intel.com> References: <1585526580-113508-1-git-send-email-nicolas.chautru@intel.com> <1585526580-113508-7-git-send-email-nicolas.chautru@intel.com> <0E78D399C70DA940A335608C6ED296D73AEF8ECE@SHSMSX104.ccr.corp.intel.com> <1183128033837D43A851F70F33ED5C576EFEAB6B@FMSMSX109.amr.corp.intel.com> <0E78D399C70DA940A335608C6ED296D73AF109BE@SHSMSX104.ccr.corp.intel.com> <1183128033837D43A851F70F33ED5C57893C3323@ORSMSX155.amr.corp.intel.com> In-Reply-To: <1183128033837D43A851F70F33ED5C57893C3323@ORSMSX155.amr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNWY1ZTFkOTAtYzM3NC00MTQxLWFjMzAtZGNiYzUwMmIwNGQ5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiV3F0bXI1ajJqV1UyS1pBQWR5OEwyOTFVaTlTZlhVd2RTc0dKajVGZU14WTBkV3FLeTFieHZjV05tdVgwYjExNiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add queue configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: Chautru, Nicolas > Sent: Wednesday, April 15, 2020 23:51 > To: Xu, Rosen ; dev@dpdk.org > Cc: Richardson, Bruce ; O'Hare, Cathal > ; akhil.goyal@nxp.com > Subject: RE: [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add > queue configuration >=20 > Hi >=20 > > From: Xu, Rosen > > Hi, > > > > > -----Original Message----- > > > From: Chautru, Nicolas > > > Sent: Tuesday, April 14, 2020 8:16 > > > To: Xu, Rosen ; dev@dpdk.org; > > > akhil.goyal@nxp.com > > > Cc: Richardson, Bruce > > > Subject: RE: [dpdk-dev] [PATCH v2 06/13] baseband/fpga_5gnr_fec: add > > > queue configuration > > > > > > Thanks Rosen for your thorough code review. Some comments in-line > below. > > > > > > > From: Xu, Rosen > > > > > > > > Hi, > > > > > > > > Could you prefix all functions name with the FPGA IP name? FPGA is > > > > a very common device name. > > > > > > > > > > I don't see such a guideline being used across all other PMDs. > > > Unsure it always help notably as this would create many long > > > function names with fpga_5gnr_fec_ added each time, and these names > > > are not exposed outside of this .c file. > > > Also some of the fpga_ prefixes would apply for either fpga_lte_fec > > > or fpga_5gnr_fec PMD. > > > If this becomes of a new guide lines we can rename every single > > > function in each existing baseband PMD in future release (not just > > > this new > > PMD). > > > > What I mentioned is that, let's take FVL for example, in our PMD, we > > name it's PMD functions with I40e_xxx, i40e is Intel NIC name, but for > > your design it named with fpga_5gnr_xxx, fpga is a common device, That > > means not Intel only provide FPGA, no sure if any other developer > > summit other FPGA based 5G acceleration IP, is it ok? > > >=20 > The new baseband PMD is indeed called "fpga_5gnr_fec" which may sound > fairly generic. > Note that that an older existing baseband PMD is currently called > "fpga_lte_fec", the new PMD is the 5G version while the previous provided > 4G capability. This depends on the user image being loaded onto the FPGA > chip. > Both these PMDs are in effect currently used by the ecosystem with the > FPGA variant from Intel called Vista Creek (based on Altera Arria10 chip)= but > there is no limitation for same driver to be used on other chip (notably = with > increased cell density on newer process) as long as the HW ring interface= is > the same or compatible image is loaded agnostically on the chip. >=20 > Let me know if unclear. >=20 >=20 >=20 It's better to name your PMD and functions as IP name prefix not FPGA name,= FPGA is a very common device. Reviewed-by: Rosen Xu