From: Konstantin Ananyev <konstantin.ananyev@huawei.com>
To: Wathsala Wathawana Vithanage <wathsala.vithanage@arm.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>,
"jerinj@marvell.com" <jerinj@marvell.com>,
"drc@linux.ibm.com" <drc@linux.ibm.com>, nd <nd@arm.com>
Subject: RE: rte_ring move head question for machines with relaxed MO (arm/ppc)
Date: Tue, 8 Oct 2024 15:45:57 +0000 [thread overview]
Message-ID: <0badc1b8ea524bf3b69d0b7b316bdc8f@huawei.com> (raw)
In-Reply-To: <PAWPR08MB89091667528C92818328DAED9F7E2@PAWPR08MB8909.eurprd08.prod.outlook.com>
> > 1. rte_ring_generic_pvt.h:
> > =====================
> >
> > pseudo-c-code // related armv8 instructions
> > -------------------- --------------------------------------
> > head.load() // ldr [head]
> > rte_smp_rmb() // dmb ishld
> > opposite_tail.load() // ldr [opposite_tail]
> > ...
> > rte_atomic32_cmpset(head, ...) // ldrex[head];... stlex[head]
> >
> >
> > 2. rte_ring_c11_pvt.h
> > =====================
> >
> > pseudo-c-code // related armv8 instructions
> > -------------------- --------------------------------------
> > head.atomic_load(relaxed) // ldr[head]
> > atomic_thread_fence(acquire) // dmb ish
> > opposite_tail.atomic_load(acquire) // lda[opposite_tail]
> > ...
> > head.atomic_cas(..., relaxed) // ldrex[haed]; ... strex[head]
> >
> >
> > 3. rte_ring_hts_elem_pvt.h
> > ==========================
> >
> > pseudo-c-code // related armv8 instructions
> > -------------------- --------------------------------------
> > head.atomic_load(acquire) // lda [head]
> > opposite_tail.load() // ldr [opposite_tail]
> > ...
> > head.atomic_cas(..., acquire) // ldaex[head]; ... strex[head]
> >
> > The questions that arose from these observations:
> > a) are all 3 approaches equivalent in terms of functionality?
> Different, lda (Load with acquire semantics) and ldr (load) are different.
I understand that, my question was:
lda {head]; ldr[tail]
vs
ldr [head]; dmb ishld; ldr [tail];
Is there any difference in terms of functionality (memory ops ordering/observability)?
>
> > b) if yes, is there any difference in terms of performance between:
> > "ldr; dmb; ldr;" vs "lda; ldr;"
> > ?
> dmb is a full barrier, performance is poor.
> I would assume (haven't measured) ldr; dmb; ldr to be less performant than lda;ldr;
Through all this mail am talking about 'dmb ishld', sorry for not being clear upfront.
>
> > c) Comapring at 1) and 2) above, combination of
> > ldr [head]; dmb; lda [opposite_tail]:
> > looks like an overkill to me. Wouldn't just:
> > ldr [head]; dmb; ldr[opposite_tail];
> > be sufficient here?
> lda [opposite_tail]: synchronizes with stlr in tail update that happens after array update.
> So, it cannot be changed to ldr.
Can you explain me a bit more here why it is not possible?
From here:
https://developer.arm.com/documentation/dui0802/b/A32-and-T32-Instructions/LDA-and-STL
"There is no requirement that a load-acquire and store-release be paired."
Do I misinterpret this statement somehow?
> lda can be replaced with ldapr (LDA with release consistency - processor consistency)
> which is more performant as lda is allowed to rise above stlr. Can be done with -mcpu=+rcpc
>
> --wathsala
>
next prev parent reply other threads:[~2024-10-08 15:46 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-08 12:58 Konstantin Ananyev
2024-10-08 15:09 ` Wathsala Wathawana Vithanage
2024-10-08 15:12 ` Wathsala Wathawana Vithanage
2024-10-08 15:45 ` Konstantin Ananyev [this message]
2024-10-08 15:56 ` Konstantin Ananyev
2024-10-09 17:27 ` Wathsala Wathawana Vithanage
2024-10-10 16:54 ` Konstantin Ananyev
2024-10-11 0:11 ` Wathsala Wathawana Vithanage
2024-10-11 14:08 ` Konstantin Ananyev
2024-10-11 15:48 ` Wathsala Wathawana Vithanage
2024-10-15 15:11 ` Konstantin Ananyev
2024-10-09 1:41 ` Wathsala Wathawana Vithanage
2024-10-09 2:22 ` Wathsala Wathawana Vithanage
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