From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from stargate3.asicdesigners.com (stargate.chelsio.com [12.32.117.8]) by dpdk.org (Postfix) with ESMTP id 2A54CBE80 for ; Wed, 3 Feb 2016 09:32:57 +0100 (CET) Received: from localhost (scalar.blr.asicdesigners.com [10.193.185.94]) by stargate3.asicdesigners.com (8.13.8/8.13.8) with ESMTP id u138WsoU024907; Wed, 3 Feb 2016 00:32:54 -0800 From: Rahul Lakkireddy To: dev@dpdk.org Date: Wed, 3 Feb 2016 14:02:27 +0530 Message-Id: <0ddc3f6d7fbbd0ae5750beecbef0d3fa0a6b87ac.1454408702.git.rahul.lakkireddy@chelsio.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: References: In-Reply-To: References: Cc: Kumar Sanghvi , Nirranjan Kirubaharan Subject: [dpdk-dev] [PATCH 06/10] cxgbe: add layer 2 table for switch action filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 03 Feb 2016 08:32:57 -0000 Add Layer 2 Table (L2T) that holds destination mac addresses and vlan ids to be modified on a packet that matches a corresponding set 'switch' action filter. Signed-off-by: Rahul Lakkireddy Signed-off-by: Kumar Sanghvi --- drivers/net/cxgbe/Makefile | 1 + drivers/net/cxgbe/base/adapter.h | 1 + drivers/net/cxgbe/base/t4_msg.h | 58 +++++++ drivers/net/cxgbe/base/t4fw_interface.h | 11 ++ drivers/net/cxgbe/cxgbe_filter.h | 1 + drivers/net/cxgbe/cxgbe_main.c | 12 ++ drivers/net/cxgbe/cxgbe_ofld.h | 9 ++ drivers/net/cxgbe/l2t.c | 261 ++++++++++++++++++++++++++++++++ drivers/net/cxgbe/l2t.h | 87 +++++++++++ 9 files changed, 441 insertions(+) create mode 100644 drivers/net/cxgbe/l2t.c create mode 100644 drivers/net/cxgbe/l2t.h diff --git a/drivers/net/cxgbe/Makefile b/drivers/net/cxgbe/Makefile index 71b654a..e98e93c 100644 --- a/drivers/net/cxgbe/Makefile +++ b/drivers/net/cxgbe/Makefile @@ -79,6 +79,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += cxgbe_main.c SRCS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += sge.c SRCS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += t4_hw.c SRCS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += clip_tbl.c +SRCS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += l2t.c # this lib depends upon: DEPDIRS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += lib/librte_eal lib/librte_ether diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h index b0234e9..c29bb98 100644 --- a/drivers/net/cxgbe/base/adapter.h +++ b/drivers/net/cxgbe/base/adapter.h @@ -339,6 +339,7 @@ struct adapter { struct clip_tbl *clipt; /* CLIP table */ unsigned int l2t_start; /* Layer 2 table start */ unsigned int l2t_end; /* Layer 2 table end */ + struct l2t_data *l2t; /* Layer 2 table */ struct tid_info tids; /* Info used to access TID related tables */ }; diff --git a/drivers/net/cxgbe/base/t4_msg.h b/drivers/net/cxgbe/base/t4_msg.h index 4b04cd0..d51edd7 100644 --- a/drivers/net/cxgbe/base/t4_msg.h +++ b/drivers/net/cxgbe/base/t4_msg.h @@ -35,6 +35,8 @@ #define T4_MSG_H enum { + CPL_L2T_WRITE_REQ = 0x12, + CPL_L2T_WRITE_RPL = 0x23, CPL_SGE_EGR_UPDATE = 0xA5, CPL_FW4_MSG = 0xC0, CPL_FW6_MSG = 0xE0, @@ -42,6 +44,11 @@ enum { CPL_TX_PKT_XT = 0xEE, }; +enum CPL_error { + CPL_ERR_NONE = 0, + CPL_ERR_TCAM_FULL = 3, +}; + enum { /* TX_PKT_XT checksum types */ TX_CSUM_TCPIP = 8, TX_CSUM_UDPIP = 9, @@ -53,6 +60,28 @@ union opcode_tid { __u8 opcode; }; +#define S_CPL_OPCODE 24 +#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) + +#define G_TID(x) ((x) & 0xFFFFFF) + +/* tid is assumed to be 24-bits */ +#define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) + +#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) + +/* extract the TID from a CPL command */ +#define GET_TID(cmd) (G_TID(be32_to_cpu(OPCODE_TID(cmd)))) + +/* partitioning of TID fields that also carry a queue id */ +#define S_TID_TID 0 +#define M_TID_TID 0x3fff +#define V_TID_TID(x) ((x) << S_TID_TID) +#define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) + +#define S_TID_QID 14 +#define V_TID_QID(x) ((x) << S_TID_QID) + struct rss_header { __u8 opcode; #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN @@ -245,6 +274,35 @@ struct cpl_rx_pkt { __be16 err_vec; }; +struct cpl_l2t_write_req { + WR_HDR; + union opcode_tid ot; + __be16 params; + __be16 l2t_idx; + __be16 vlan; + __u8 dst_mac[6]; +}; + +/* cpl_l2t_write_req.params fields */ +#define S_L2T_W_PORT 8 +#define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) + +#define S_L2T_W_LPBK 10 +#define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) + +#define S_L2T_W_ARPMISS 11 +#define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) + +#define S_L2T_W_NOREPLY 15 +#define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) + +struct cpl_l2t_write_rpl { + RSS_HDR + union opcode_tid ot; + __u8 status; + __u8 rsvd[3]; +}; + /* rx_pkt.l2info fields */ #define S_RXF_UDP 22 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h index cbf9f32..8a8652a 100644 --- a/drivers/net/cxgbe/base/t4fw_interface.h +++ b/drivers/net/cxgbe/base/t4fw_interface.h @@ -82,6 +82,7 @@ enum fw_memtype { ********************************/ enum fw_wr_opcodes { + FW_TP_WR = 0x05, FW_ETH_TX_PKT_WR = 0x08, FW_ETH_TX_PKTS_WR = 0x09, }; @@ -101,6 +102,11 @@ struct fw_wr_hdr { #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) +/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER + */ +#define S_FW_WR_ATOMIC 23 +#define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) + /* work request immediate data length (hi) */ #define S_FW_WR_IMMDLEN 0 @@ -117,6 +123,11 @@ struct fw_wr_hdr { #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) +/* flow context identifier (lo) + */ +#define S_FW_WR_FLOWID 8 +#define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) + /* length in units of 16-bytes (lo) */ #define S_FW_WR_LEN16 0 diff --git a/drivers/net/cxgbe/cxgbe_filter.h b/drivers/net/cxgbe/cxgbe_filter.h index bb4b367..933496a 100644 --- a/drivers/net/cxgbe/cxgbe_filter.h +++ b/drivers/net/cxgbe/cxgbe_filter.h @@ -219,6 +219,7 @@ struct filter_entry { u32 pending:1; /* filter action is pending FW reply */ struct filter_ctx *ctx; /* caller's completion hook */ struct clip_entry *clipt; /* CLIP Table entry for IPv6 */ + struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ struct rte_eth_dev *dev; /* Port's rte eth device */ /* This will store the actual tid */ diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c index 5960d9a..63c6318 100644 --- a/drivers/net/cxgbe/cxgbe_main.c +++ b/drivers/net/cxgbe/cxgbe_main.c @@ -67,6 +67,7 @@ #include "t4_msg.h" #include "cxgbe.h" #include "clip_tbl.h" +#include "l2t.h" /** * Allocate a chunk of memory. The allocated memory is cleared. @@ -116,6 +117,10 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, const struct cpl_fw6_msg *msg = (const void *)rsp; t4_handle_fw_rpl(q->adapter, msg->data); + } else if (opcode == CPL_L2T_WRITE_RPL) { + const struct cpl_l2t_write_rpl *p = (const void *)rsp; + + do_l2t_write_rpl(q->adapter, p); } else { dev_err(adapter, "unexpected CPL %#x on FW event queue\n", opcode); @@ -1224,6 +1229,7 @@ void cxgbe_close(struct adapter *adapter) if (adapter->flags & FULL_INIT_DONE) { tid_free(&adapter->tids); t4_cleanup_clip_tbl(adapter); + t4_cleanup_l2t(adapter); t4_intr_disable(adapter); t4_sge_tx_monitor_stop(adapter); t4_free_sge_resources(adapter); @@ -1375,6 +1381,12 @@ allocate_mac: dev_warn(adapter, "could not allocate CLIP. Continuing\n"); } + adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); + if (!adapter->l2t) { + /* We tolerate a lack of L2T, giving up some functionality */ + dev_warn(adapter, "could not allocate L2T. Continuing\n"); + } + if (tid_init(&adapter->tids) < 0) { /* Disable filtering support */ dev_warn(adapter, "could not allocate TID table, " diff --git a/drivers/net/cxgbe/cxgbe_ofld.h b/drivers/net/cxgbe/cxgbe_ofld.h index 3bcb648..19971e7 100644 --- a/drivers/net/cxgbe/cxgbe_ofld.h +++ b/drivers/net/cxgbe/cxgbe_ofld.h @@ -38,6 +38,15 @@ #include "cxgbe_filter.h" +#define INIT_TP_WR(w, tid) do { \ + (w)->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_TP_WR) | \ + V_FW_WR_IMMDLEN(sizeof(*w) - sizeof(w->wr))); \ + (w)->wr.wr_mid = cpu_to_be32( \ + V_FW_WR_LEN16(DIV_ROUND_UP(sizeof(*w), 16)) | \ + V_FW_WR_FLOWID(tid)); \ + (w)->wr.wr_lo = cpu_to_be64(0); \ +} while (0) + /* * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. */ diff --git a/drivers/net/cxgbe/l2t.c b/drivers/net/cxgbe/l2t.c new file mode 100644 index 0000000..cf36150 --- /dev/null +++ b/drivers/net/cxgbe/l2t.c @@ -0,0 +1,261 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2015-2016 Chelsio Communications. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Chelsio Communications nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "common.h" +#include "l2t.h" + +/** + * cxgbe_l2t_release - Release associated L2T entry + * @e: L2T entry to release + * + * Releases ref count and frees up an L2T entry from L2T table + */ +void cxgbe_l2t_release(struct l2t_entry *e) +{ + if (rte_atomic32_read(&e->refcnt) != 0) + rte_atomic32_dec(&e->refcnt); +} + +/** + * Process a CPL_L2T_WRITE_RPL. Note that the TID in the reply is really + * the L2T index it refers to. + */ +void do_l2t_write_rpl(struct adapter *adap, const struct cpl_l2t_write_rpl *rpl) +{ + struct l2t_data *d = adap->l2t; + unsigned int tid = GET_TID(rpl); + unsigned int l2t_idx = tid % L2T_SIZE; + + if (unlikely(rpl->status != CPL_ERR_NONE)) { + dev_err(adap, + "Unexpected L2T_WRITE_RPL status %u for entry %u\n", + rpl->status, l2t_idx); + return; + } + + if (tid & F_SYNC_WR) { + struct l2t_entry *e = &d->l2tab[l2t_idx - d->l2t_start]; + + t4_os_lock(&e->lock); + if (e->state != L2T_STATE_SWITCHING) + e->state = L2T_STATE_VALID; + t4_os_unlock(&e->lock); + } +} + +/** + * Write an L2T entry. Must be called with the entry locked. + * The write may be synchronous or asynchronous. + */ +static int write_l2e(struct rte_eth_dev *dev, struct l2t_entry *e, int sync, + bool loopback, bool arpmiss) +{ + struct adapter *adap = ethdev2adap(dev); + struct l2t_data *d = adap->l2t; + struct rte_mbuf *mbuf; + struct cpl_l2t_write_req *req; + struct sge_ctrl_txq *ctrlq; + unsigned int l2t_idx = e->idx + d->l2t_start; + unsigned int port_id = ethdev2pinfo(dev)->port_id; + int i; + + ctrlq = &adap->sge.ctrlq[port_id]; + mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool); + if (!mbuf) + return -ENOMEM; + + mbuf->data_len = sizeof(*req); + mbuf->pkt_len = mbuf->data_len; + + req = rte_pktmbuf_mtod(mbuf, struct cpl_l2t_write_req *); + INIT_TP_WR(req, 0); + + OPCODE_TID(req) = + cpu_to_be32(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, + l2t_idx | V_SYNC_WR(sync) | + V_TID_QID(adap->sge.fw_evtq.abs_id))); + req->params = cpu_to_be16(V_L2T_W_PORT(e->lport) | + V_L2T_W_LPBK(loopback) | + V_L2T_W_ARPMISS(arpmiss) | + V_L2T_W_NOREPLY(!sync)); + req->l2t_idx = cpu_to_be16(l2t_idx); + req->vlan = cpu_to_be16(e->vlan); + rte_memcpy(req->dst_mac, e->dmac, ETHER_ADDR_LEN); + + if (loopback) { + for (i = 0; i < ETHER_ADDR_LEN; i++) + req->dst_mac[i] = 0; + } + + t4_mgmt_tx(ctrlq, mbuf); + + if (sync && e->state != L2T_STATE_SWITCHING) + e->state = L2T_STATE_SYNC_WRITE; + + return 0; +} + +/** + * find_or_alloc_l2e - Find/Allocate a free L2T entry + * @d: L2T table + * @vlan: VLAN id to compare/add + * @port: port id to compare/add + * @dmac: Destination MAC address to compare/add + * Returns pointer to the L2T entry found/created + * + * Finds/Allocates an L2T entry to be used by switching rule of a filter. + */ +static struct l2t_entry *find_or_alloc_l2e(struct l2t_data *d, u16 vlan, + u8 port, u8 *dmac) +{ + struct l2t_entry *end, *e; + struct l2t_entry *first_free = NULL; + + for (e = &d->l2tab[0], end = &d->l2tab[d->l2t_size]; e != end; ++e) { + if (rte_atomic32_read(&e->refcnt) == 0) { + if (!first_free) + first_free = e; + } else { + if (e->state == L2T_STATE_SWITCHING) { + if ((!memcmp(e->dmac, dmac, ETHER_ADDR_LEN)) && + (e->vlan == vlan) && (e->lport == port)) + goto exists; + } + } + } + + if (first_free) { + e = first_free; + goto found; + } + + return NULL; + +found: + e->state = L2T_STATE_UNUSED; + +exists: + return e; +} + +static struct l2t_entry *t4_l2t_alloc_switching(struct rte_eth_dev *dev, + u16 vlan, u8 port, + u8 *eth_addr) +{ + struct adapter *adap = ethdev2adap(dev); + struct l2t_data *d = adap->l2t; + struct l2t_entry *e; + int ret; + + t4_os_write_lock(&d->lock); + e = find_or_alloc_l2e(d, vlan, port, eth_addr); + if (e) { + t4_os_lock(&e->lock); + if (!rte_atomic32_read(&e->refcnt)) { + e->state = L2T_STATE_SWITCHING; + e->vlan = vlan; + e->lport = port; + rte_memcpy(e->dmac, eth_addr, ETHER_ADDR_LEN); + rte_atomic32_set(&e->refcnt, 1); + ret = write_l2e(dev, e, 0, !L2T_LPBK, !L2T_ARPMISS); + if (ret < 0) { + dev_debug(adap, "Failed to write L2T entry: %d", + ret); + e = NULL; + } + } else { + rte_atomic32_inc(&e->refcnt); + } + t4_os_unlock(&e->lock); + } + t4_os_write_unlock(&d->lock); + + return e; +} + +/** + * cxgbe_l2t_alloc_switching - Allocate a L2T entry for switching rule + * @dev: rte_eth_dev pointer + * @vlan: VLAN Id + * @port: Associated port + * @dmac: Destination MAC address to add to L2T + * Returns pointer to the allocated l2t entry + * + * Allocates a L2T entry for use by switching rule of a filter + */ +struct l2t_entry *cxgbe_l2t_alloc_switching(struct rte_eth_dev *dev, u16 vlan, + u8 port, u8 *dmac) +{ + return t4_l2t_alloc_switching(dev, vlan, port, dmac); +} + +/** + * Initialize L2 Table + */ +struct l2t_data *t4_init_l2t(unsigned int l2t_start, unsigned int l2t_end) +{ + unsigned int l2t_size; + unsigned int i; + struct l2t_data *d; + + if (l2t_start >= l2t_end || l2t_end >= L2T_SIZE) + return NULL; + l2t_size = l2t_end - l2t_start + 1; + + d = t4_os_alloc(sizeof(*d) + l2t_size * sizeof(struct l2t_entry)); + if (!d) + return NULL; + + d->l2t_start = l2t_start; + d->l2t_size = l2t_size; + + t4_os_rwlock_init(&d->lock); + + for (i = 0; i < d->l2t_size; ++i) { + d->l2tab[i].idx = i; + d->l2tab[i].state = L2T_STATE_UNUSED; + t4_os_lock_init(&d->l2tab[i].lock); + rte_atomic32_set(&d->l2tab[i].refcnt, 0); + } + + return d; +} + +/** + * Cleanup L2 Table + */ +void t4_cleanup_l2t(struct adapter *adap) +{ + if (adap->l2t) + t4_os_free(adap->l2t); +} diff --git a/drivers/net/cxgbe/l2t.h b/drivers/net/cxgbe/l2t.h new file mode 100644 index 0000000..a6bb9f7 --- /dev/null +++ b/drivers/net/cxgbe/l2t.h @@ -0,0 +1,87 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2015-2016 Chelsio Communications. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Chelsio Communications nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CXGBE_L2T_H_ +#define _CXGBE_L2T_H_ + +#include "t4_msg.h" + +enum { + L2T_SIZE = 4096 /* # of L2T entries */ +}; + +enum { + L2T_STATE_VALID, /* entry is up to date */ + L2T_STATE_SYNC_WRITE, /* synchronous write of entry underway */ + + /* when state is one of the below the entry is not hashed */ + L2T_STATE_SWITCHING, /* entry is being used by a switching filter */ + L2T_STATE_UNUSED /* entry not in use */ +}; + +/* + * State for the corresponding entry of the HW L2 table. + */ +struct l2t_entry { + u16 state; /* entry state */ + u16 idx; /* entry index within in-memory table */ + u32 addr[4]; /* next hop IP or IPv6 address */ + u16 vlan; /* VLAN TCI (id: bits 0-11, prio: 13-15 */ + u8 lport; /* destination port */ + u8 dmac[ETHER_ADDR_LEN]; /* destination MAC address */ + rte_spinlock_t lock; /* entry lock */ + rte_atomic32_t refcnt; /* entry reference count */ +}; + +struct l2t_data { + unsigned int l2t_start; /* start index of our piece of the L2T */ + unsigned int l2t_size; /* number of entries in l2tab */ + rte_rwlock_t lock; /* table rw lock */ + struct l2t_entry l2tab[0]; /* MUST BE LAST */ +}; + +#define L2T_LPBK true +#define L2T_ARPMISS true + +/* identifies sync vs async L2T_WRITE_REQs */ +#define S_SYNC_WR 12 +#define V_SYNC_WR(x) ((x) << S_SYNC_WR) +#define F_SYNC_WR V_SYNC_WR(1) + +struct l2t_data *t4_init_l2t(unsigned int l2t_start, unsigned int l2t_end); +void t4_cleanup_l2t(struct adapter *adap); +struct l2t_entry *cxgbe_l2t_alloc_switching(struct rte_eth_dev *dev, u16 vlan, + u8 port, u8 *dmac); +void cxgbe_l2t_release(struct l2t_entry *e); +void do_l2t_write_rpl(struct adapter *p, const struct cpl_l2t_write_rpl *rpl); +#endif /* _CXGBE_L2T_H_ */ -- 2.5.3