From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id AE3F52BCD for ; Mon, 5 Dec 2016 20:40:56 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP; 05 Dec 2016 11:40:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,749,1477983600"; d="scan'208";a="13948291" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.237.220.29]) ([10.237.220.29]) by orsmga002.jf.intel.com with ESMTP; 05 Dec 2016 11:40:33 -0800 To: Wei Dai , helin.zhang@intel.com, konstantin.ananyev@intel.com References: <1480833100-48545-1-git-send-email-wei.dai@intel.com> <1480833100-48545-27-git-send-email-wei.dai@intel.com> Cc: dev@dpdk.org From: Ferruh Yigit Message-ID: <10604e95-4011-00d4-cc4f-42bf0feacf3d@intel.com> Date: Mon, 5 Dec 2016 19:40:32 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <1480833100-48545-27-git-send-email-wei.dai@intel.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH 27/29] net/ixgbe/base: add write flush required by Inphi X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Dec 2016 19:40:57 -0000 On 12/4/2016 6:31 AM, Wei Dai wrote: > This patch updates Inphi configuration to flush the register write with Do we really need to mention from Inphi here? If so, can you please explain what it is? > a reg read. Inphi is configured in ixgbe_setup_mac_link_sfp_x550a. > The Inphy setup flow has been updated to read configuration reg, write > only linear/non-linear, and then read (write flush). Also patch does [1] seems not mentioned in the commit log, can you please add information for it? [1] > + reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | > + (IXGBE_CS4227_EDC_MODE_SR << 1)); > > Signed-off-by: Wei Dai > --- > drivers/net/ixgbe/base/ixgbe_x550.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c > index 4a98530..a57ba74 100644 > --- a/drivers/net/ixgbe/base/ixgbe_x550.c > +++ b/drivers/net/ixgbe/base/ixgbe_x550.c > @@ -2834,12 +2834,26 @@ s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, > > /* Configure CS4227/CS4223 LINE side to proper mode. */ > reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; > + > + ret_val = hw->phy.ops.read_reg(hw, reg_slice, > + IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); > + > + if (ret_val != IXGBE_SUCCESS) > + return ret_val; > + > + reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | > + (IXGBE_CS4227_EDC_MODE_SR << 1)); > + > if (setup_linear) > reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; > else > reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; > ret_val = hw->phy.ops.write_reg(hw, reg_slice, > IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); > + > + /* Flush previous write with a read */ > + ret_val = hw->phy.ops.read_reg(hw, reg_slice, > + IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); > } > return ret_val; > } >