From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 48BB4A046B for ; Wed, 26 Jun 2019 13:54:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B93E81E20; Wed, 26 Jun 2019 13:54:21 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id E02CCDED for ; Wed, 26 Jun 2019 13:54:18 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2019 04:54:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,419,1557212400"; d="scan'208";a="188627271" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.237.221.30]) ([10.237.221.30]) by fmsmga002.fm.intel.com with ESMTP; 26 Jun 2019 04:54:16 -0700 To: Ziyang Xuan , dev@dpdk.org Cc: cloud.wangxiaoyun@huawei.com, shahar.belkar@huawei.com, tanya.brokhman@huawei.com, luoxianjun@huawei.com References: <691dcc833654d7e8a666e88ea07dae95a4951230.1560958308.git.xuanziyang2@huawei.com> From: Ferruh Yigit Openpgp: preference=signencrypt Autocrypt: addr=ferruh.yigit@intel.com; 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WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: <691dcc833654d7e8a666e88ea07dae95a4951230.1560958308.git.xuanziyang2@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v5 14/15] net/hinic: add tx/rx package burst X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 6/19/2019 5:20 PM, Ziyang Xuan wrote: > This patch add package sending and receiving function codes. > > Signed-off-by: Ziyang Xuan <...> > @@ -543,6 +728,113 @@ void hinic_free_all_rx_skbs(struct hinic_rxq *rxq) > } > } > > +static inline void hinic_rq_cqe_be_to_cpu32(void *dst_le32, > + volatile void *src_be32) > +{ > +#ifndef __ARM64_NEON__ > + volatile __m128i *wqe_be = (volatile __m128i *)src_be32; > + __m128i *wqe_le = (__m128i *)dst_le32; > + __m128i shuf_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10, > + 11, 4, 5, 6, 7, 0, 1, 2, 3); > + > + /* l2nic just use first 128 bits */ > + wqe_le[0] = _mm_shuffle_epi8(wqe_be[0], shuf_mask); > +#else > + volatile uint8x16_t *wqe_be = (volatile uint8x16_t *)src_be32; > + uint8x16_t *wqe_le = (uint8x16_t *)dst_le32; > + const uint8x16_t shuf_mask = {3, 2, 1, 0, 7, 6, 5, 4, 11, 10, > + 9, 8, 15, 14, 13, 12}; > + > + /* l2nic just use first 128 bits */ > + wqe_le[0] = vqtbl1q_u8(wqe_be[0], shuf_mask); > +#endif > +} I am aware documentation says only arm64 and x86_64 are supported and default config files default values implemented that way, still I believe it is safer to not just assume it is either one or other. What do you think explicitly check X86_64 too, as done for ARM64?