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[213.41.180.237]) by mx.google.com with ESMTPSA id t5sm6398wjw.15.2014.02.19.04.12.30 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Feb 2014 04:12:30 -0800 (PST) Resent-From: Thomas Monjalon Resent-To: dev@dpdk.org Resent-Date: Wed, 19 Feb 2014 13:12:28 +0100 Resent-Message-ID: <201402191312.28986.didier.pallard@6wind.com> Received: by 10.76.82.162 with SMTP id j2csp6770oay; Wed, 19 Feb 2014 03:59:37 -0800 (PST) X-Received: by 10.180.219.66 with SMTP id pm2mr1059631wic.60.1392811177268; Wed, 19 Feb 2014 03:59:37 -0800 (PST) Received: from mail-wi0-f181.google.com (mail-wi0-f181.google.com [209.85.212.181]) by mx.google.com with ESMTPS id ck5si17783312wjc.84.2014.02.19.03.59.36 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 19 Feb 2014 03:59:37 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.181 is neither permitted nor denied by best guess record for domain of didier.pallard@6wind.com) client-ip=209.85.212.181; Received: by mail-wi0-f181.google.com with SMTP id hi5so488936wib.2 for ; Wed, 19 Feb 2014 03:59:36 -0800 (PST) X-Received: by 10.180.211.208 with SMTP id ne16mr1034304wic.21.1392811176530; Wed, 19 Feb 2014 03:59:36 -0800 (PST) Received: from pala.dev.6wind.com (6wind.net2.nerim.net. [213.41.180.237]) by mx.google.com with ESMTPSA id fm3sm51219809wib.8.2014.02.19.03.59.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Feb 2014 03:59:35 -0800 (PST) From: Didier Pallard To: thomas.monjalon@6wind.com Date: Wed, 19 Feb 2014 12:59:22 +0100 Message-Id: <1392811162-28527-2-git-send-email-didier.pallard@6wind.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1392811162-28527-1-git-send-email-didier.pallard@6wind.com> References: <1392811162-28527-1-git-send-email-didier.pallard@6wind.com> X-Length: 8890 X-UID: 25249 Subject: [dpdk-dev] [RFC PATCH 2/2] ixgbe: release software locked semaphores on initialization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Feb 2014 12:11:07 -0000 It may happen that DPDK application gets killed while having acquired locks on the ethernet hardware, causing these locks to be never released. On next restart of the application, DPDK skip those ports because it can not acquire the lock, this may cause some ports (or even complete board if SMBI is locked) to be inaccessible from DPDK application until reboot of the hardware. This patch release locks that are supposed to be locked due to an improper exit of the application. Signed-off-by: Didier Pallard --- lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c | 30 +++++++++++++++++++++++++++ lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c | 29 ++++++++++++++++++++++++++ lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c | 33 ++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+) diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c index a9d1b9d..8e2ca1c 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c @@ -115,6 +115,7 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) struct ixgbe_mac_info *mac = &hw->mac; struct ixgbe_phy_info *phy = &hw->phy; s32 ret_val; + u16 mask; DEBUGFUNC("ixgbe_init_ops_82598"); @@ -166,6 +167,35 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) /* Manageability interface */ mac->ops.set_fw_drv_ver = NULL; + /* Get bus info */ + mac->ops.get_bus_info(hw); + + /* Ensure that all locks are released before first NVM or PHY access */ + + /* + * Phy lock should not fail in this early stage. If this is the case, + * it is due to an improper exit of the application. + * So force the release of the faulty lock. Release of common lock + * is done automatically by swfw_sync function. + */ + mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; + if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { + DEBUGOUT1("SWFW phy%d lock released", hw->bus.func); + } + hw->mac.ops.release_swfw_sync(hw, mask); + + /* + * Those one are more tricky since they are common to all ports; but + * swfw_sync retries last long enough (1s) to be almost sure that if + * lock can not be taken it is due to an improper lock of the + * semaphore. + */ + mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; + if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { + DEBUGOUT("SWFW common locks released"); + } + hw->mac.ops.release_swfw_sync(hw, mask); + return ret_val; } diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c index db07789..ca91967 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c @@ -223,6 +223,7 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) struct ixgbe_phy_info *phy = &hw->phy; struct ixgbe_eeprom_info *eeprom = &hw->eeprom; s32 ret_val; + u16 mask; DEBUGFUNC("ixgbe_init_ops_82599"); @@ -291,6 +292,34 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) /* Manageability interface */ mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; + /* Get bus info */ + mac->ops.get_bus_info(hw); + + /* Ensure that all locks are released before first NVM or PHY access */ + + /* + * Phy lock should not fail in this early stage. If this is the case, + * it is due to an improper exit of the application. + * So force the release of the faulty lock. Release of common lock + * is done automatically by swfw_sync function. + */ + mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; + if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { + DEBUGOUT1("SWFW phy%d lock released", hw->bus.func); + } + hw->mac.ops.release_swfw_sync(hw, mask); + + /* + * Those one are more tricky since they are common to all ports; but + * swfw_sync retries last long enough (1s) to be almost sure that if + * lock can not be taken it is due to an improper lock of the + * semaphore. + */ + mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; + if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { + DEBUGOUT("SWFW common locks released"); + } + hw->mac.ops.release_swfw_sync(hw, mask); return ret_val; } diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c index d3e1730..607c9c7 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c @@ -55,6 +55,7 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) struct ixgbe_phy_info *phy = &hw->phy; struct ixgbe_eeprom_info *eeprom = &hw->eeprom; s32 ret_val; + u16 mask; DEBUGFUNC("ixgbe_init_ops_X540"); @@ -141,6 +142,38 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) /* Manageability interface */ mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; + /* Get bus info */ + mac->ops.get_bus_info(hw); + + /* Ensure that all locks are released before first NVM or PHY access */ + + /* + * Phy lock should not fail in this early stage. If this is the case, + * it is due to an improper exit of the application. + * So force the release of the faulty lock. + */ + mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; + if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { + if (ixgbe_get_swfw_sync_semaphore(hw) < 0) { + DEBUGOUT("SMBI lock released"); + } + ixgbe_release_swfw_sync_semaphore(hw); + DEBUGOUT1("SWFW phy%d lock released", hw->bus.func); + } + hw->mac.ops.release_swfw_sync(hw, mask); + + /* + * Those one are more tricky since they are common to all ports; but + * swfw_sync retries last long enough (1s) to be almost sure that if + * lock can not be taken it is due to an improper lock of the + * semaphore. + */ + mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; + if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { + DEBUGOUT("SWFW common locks released"); + } + hw->mac.ops.release_swfw_sync(hw, mask); + return ret_val; } -- 1.7.10.4