From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 7CBFC30D for ; Wed, 2 Jul 2014 05:10:17 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 01 Jul 2014 20:10:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,586,1400050800"; d="scan'208";a="537515003" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga001.jf.intel.com with ESMTP; 01 Jul 2014 20:10:36 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s623AYSI013186; Wed, 2 Jul 2014 11:10:34 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s623AVcS002594; Wed, 2 Jul 2014 11:10:33 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s623AVZA002590; Wed, 2 Jul 2014 11:10:31 +0800 From: Helin Zhang To: dev@dpdk.org Date: Wed, 2 Jul 2014 11:10:25 +0800 Message-Id: <1404270625-2470-3-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.0.7 In-Reply-To: <1404270625-2470-1-git-send-email-helin.zhang@intel.com> References: <1404270625-2470-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH 2/2] i40e: add required steps in TX queue enable, disable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Jul 2014 03:10:18 -0000 Hardware specification changed recently which requires to set or clear TX queue disable flags before actually enabling or disabling a specific TX queue. 'QTX_HEAD' register needs to be cleared before setting the QENA_REQ flag. Signed-off-by: Helin Zhang Acked-by: Jijiang Liu Acked-by: Jing Chen --- lib/librte_pmd_i40e/i40e_ethdev.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c index 6624586..9ed31b5 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -85,6 +85,8 @@ #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ +#define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */ + #define I40E_RSS_OFFLOAD_ALL ( \ ETH_RSS_NONF_IPV4_UDP | \ ETH_RSS_NONF_IPV4_TCP | \ @@ -2780,6 +2782,13 @@ i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) uint32_t reg; uint16_t j; + /** + * Set or clear TX Queue Disable flags, + * which is required by hardware. + */ + i40e_pre_tx_queue_cfg(hw, q_idx, on); + rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US); + /* Wait until the request is finished */ for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); @@ -2793,6 +2802,8 @@ i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) if (on) { if (reg & I40E_QTX_ENA_QENA_STAT_MASK) return I40E_SUCCESS; /* already on, skip next steps */ + + I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0); reg |= I40E_QTX_ENA_QENA_REQ_MASK; } else { if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) @@ -2821,8 +2832,10 @@ i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) (on ? "enable" : "disable"), q_idx); return I40E_ERR_TIMEOUT; } + return I40E_SUCCESS; } + /* Swith on or off the tx queues */ static int i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on) -- 1.8.1.4