From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id A6E327DF3 for ; Fri, 26 Sep 2014 07:57:31 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 25 Sep 2014 22:54:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,603,1406617200"; d="scan'208";a="597109889" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga001.fm.intel.com with ESMTP; 25 Sep 2014 23:03:50 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s8Q63nXV027978; Fri, 26 Sep 2014 14:03:49 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s8Q63kUc012937; Fri, 26 Sep 2014 14:03:48 +0800 Received: (from wujingji@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8Q63kPx012933; Fri, 26 Sep 2014 14:03:46 +0800 From: Jingjing Wu To: dev@dpdk.org Date: Fri, 26 Sep 2014 14:03:21 +0800 Message-Id: <1411711418-12881-4-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1411711418-12881-1-git-send-email-jingjing.wu@intel.com> References: <1411711418-12881-1-git-send-email-jingjing.wu@intel.com> Subject: [dpdk-dev] [PATCH v3 03/20] i40e: initialize flexible payload setting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Sep 2014 05:57:32 -0000 set flexible payload related registers to default value at initialization time. Signed-off-by: Jingjing Wu Acked-by: Chen Jing D(Mark) Acked-by: Helin Zhang --- lib/librte_pmd_i40e/i40e_ethdev.c | 33 ++++++++++++++++++++++++++ lib/librte_pmd_i40e/i40e_fdir.c | 49 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c index da131a8..a3f25e6 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -336,6 +336,32 @@ static struct rte_driver rte_i40e_driver = { PMD_REGISTER_DRIVER(rte_i40e_driver); +/* + * Initialize registers for flexible payload, which should be set by NVM. + * This should be removed from code once is fixed in NVM. + */ +static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw) +{ + /* GLQF_ORT Registers */ + I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D); + + /* GLQF_PIT Registers */ + I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480); + I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440); + + /* GL_PRS_FVBM Registers */ + I40E_WRITE_REG(hw, I40E_GL_PRS_FVBM(1), 0x8000035B); +} + static int eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv, struct rte_eth_dev *dev) @@ -399,6 +425,13 @@ eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv, return ret; } + /* + * To work around the NVM issue,initialize registers + * for flexible payload by software. + * It should be removed once issues are fixed in NVM. + */ + i40e_flex_payload_reg_init(hw); + /* Initialize the parameters for adminq */ i40e_init_adminq_parameter(hw); ret = i40e_init_adminq(hw); diff --git a/lib/librte_pmd_i40e/i40e_fdir.c b/lib/librte_pmd_i40e/i40e_fdir.c index 3d8faa0..a3e6bd7 100644 --- a/lib/librte_pmd_i40e/i40e_fdir.c +++ b/lib/librte_pmd_i40e/i40e_fdir.c @@ -109,6 +109,53 @@ i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq) } /* + * Initialize the configuration about bytes stream extracted as flexible payload + * and mask setting + */ +static inline void +i40e_init_flx_pld(struct i40e_pf *pf) +{ + uint8_t pctype;; + struct i40e_hw *hw = I40E_PF_TO_HW(pf); + + /* + * Define the bytes stream extracted as flexible payload in + * field vector. By default, select 8 words from the beginning + * of payload as flexible payload. + */ + memset(pf->fdir.flex_set, 0, sizeof(pf->fdir.flex_set)); + + /* initialize the flexible payload for L2 payload*/ + pf->fdir.flex_set[0][0].offset = 0; + pf->fdir.flex_set[0][0].size = 8; + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(0), 0x0000C900); + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(1), 0x0000FC29);/*non-used*/ + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(2), 0x0000FC2A);/*non-used*/ + + /* initialize the flexible payload for L3 payload*/ + pf->fdir.flex_set[1][0].offset = 0; + pf->fdir.flex_set[1][0].size = 8; + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(3), 0x0000C900); + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(4), 0x0000FC29);/*non-used*/ + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(5), 0x0000FC2A);/*non-used*/ + + /* initialize the flexible payload for L4 payload*/ + pf->fdir.flex_set[2][0].offset = 0; + pf->fdir.flex_set[2][0].size = 8; + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(6), 0x0000C900); + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(7), 0x0000FC29);/*non-used*/ + I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(8), 0x0000FC2A);/*non-used*/ + + /* initialize the masks */ + for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; + pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) { + I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0); + I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, 0), 0); + I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, 1), 0); + } +} + +/* * i40e_fdir_setup - reserve and initialize the Flow Director resources * @pf: board private structure */ @@ -182,6 +229,8 @@ i40e_fdir_setup(struct i40e_pf *pf) goto fail_mem; } + i40e_init_flx_pld(pf); + /* reserve memory for the fdir programming packet */ snprintf(z_name, sizeof(z_name), "%s_%s_%d", eth_dev->driver->pci_drv.name, -- 1.8.1.4