From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 6425C5A8F for ; Thu, 29 Jan 2015 06:29:37 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 28 Jan 2015 21:26:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,484,1418112000"; d="scan'208";a="677806788" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga002.jf.intel.com with ESMTP; 28 Jan 2015 21:29:35 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t0T5TUp9022465; Thu, 29 Jan 2015 13:29:30 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t0T5TSUh013637; Thu, 29 Jan 2015 13:29:30 +0800 Received: (from wujingji@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t0T5TSKG013633; Thu, 29 Jan 2015 13:29:28 +0800 From: Jingjing Wu To: dev@dpdk.org Date: Thu, 29 Jan 2015 13:29:11 +0800 Message-Id: <1422509365-13596-2-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1422509365-13596-1-git-send-email-jingjing.wu@intel.com> References: <1422509365-13596-1-git-send-email-jingjing.wu@intel.com> Subject: [dpdk-dev] [PATCH 01/15] ixgbe: migrate flow director filter operations (add/delete/update) to new API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Jan 2015 05:29:38 -0000 This patch changes the add/delete/update operations to be implemented through filter_ctrl API and RTE_ETH_FILTER_ADD/RTE_ETH_FILTER_DELETE/RTE_ETH_FILTER_UPDATE ops. It also removes the callback functions: - ixgbe_eth_dev_ops.fdir_add_signature_filter - ixgbe_eth_dev_ops.fdir_update_signature_filter - ixgbe_eth_dev_ops.fdir_remove_signature_filter - ixgbe_eth_dev_ops.fdir_add_perfect_filter - ixgbe_eth_dev_ops.fdir_update_perfect_filter - ixgbe_eth_dev_ops.fdir_remove_perfect_filter Signed-off-by: Jingjing Wu --- lib/librte_pmd_ixgbe/ixgbe_ethdev.c | 9 +- lib/librte_pmd_ixgbe/ixgbe_ethdev.h | 23 +- lib/librte_pmd_ixgbe/ixgbe_fdir.c | 927 ++++++++++++++++++------------------ 3 files changed, 477 insertions(+), 482 deletions(-) diff --git a/lib/librte_pmd_ixgbe/ixgbe_ethdev.c b/lib/librte_pmd_ixgbe/ixgbe_ethdev.c index b341dd0..c3a76e6 100644 --- a/lib/librte_pmd_ixgbe/ixgbe_ethdev.c +++ b/lib/librte_pmd_ixgbe/ixgbe_ethdev.c @@ -360,13 +360,7 @@ static struct eth_dev_ops ixgbe_eth_dev_ops = { .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter, .set_queue_rate_limit = ixgbe_set_queue_rate_limit, .set_vf_rate_limit = ixgbe_set_vf_rate_limit, - .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter, - .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter, - .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter, .fdir_infos_get = ixgbe_fdir_info_get, - .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter, - .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter, - .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter, .fdir_set_masks = ixgbe_fdir_set_masks, .reta_update = ixgbe_dev_rss_reta_update, .reta_query = ixgbe_dev_rss_reta_query, @@ -4213,6 +4207,9 @@ ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, case RTE_ETH_FILTER_ETHERTYPE: ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); break; + case RTE_ETH_FILTER_FDIR: + ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); + break; default: PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", filter_type); diff --git a/lib/librte_pmd_ixgbe/ixgbe_ethdev.h b/lib/librte_pmd_ixgbe/ixgbe_ethdev.h index 1383194..d92e54a 100644 --- a/lib/librte_pmd_ixgbe/ixgbe_ethdev.h +++ b/lib/librte_pmd_ixgbe/ixgbe_ethdev.h @@ -309,29 +309,9 @@ int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, */ int ixgbe_fdir_configure(struct rte_eth_dev *dev); -int ixgbe_fdir_add_signature_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint8_t queue); - -int ixgbe_fdir_update_signature_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint8_t queue); - -int ixgbe_fdir_remove_signature_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter); - void ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir *fdir); -int ixgbe_fdir_add_perfect_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint16_t soft_id, - uint8_t queue, uint8_t drop); - -int ixgbe_fdir_update_perfect_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter,uint16_t soft_id, - uint8_t queue, uint8_t drop); - -int ixgbe_fdir_remove_perfect_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint16_t soft_id); - int ixgbe_fdir_set_masks(struct rte_eth_dev *dev, struct rte_fdir_masks *fdir_masks); @@ -355,4 +335,7 @@ void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev); int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev); uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val); + +int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev, + enum rte_filter_op filter_op, void *arg); #endif /* _IXGBE_ETHDEV_H_ */ diff --git a/lib/librte_pmd_ixgbe/ixgbe_fdir.c b/lib/librte_pmd_ixgbe/ixgbe_fdir.c index cfcb515..e682d14 100644 --- a/lib/librte_pmd_ixgbe/ixgbe_fdir.c +++ b/lib/librte_pmd_ixgbe/ixgbe_fdir.c @@ -62,7 +62,28 @@ #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */ #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */ #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */ - +#define IXGBE_FDIRCMD_CMD_INTERVAL_US 10 + +static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash); +static int ixgbe_fdir_filter_to_atr_input( + const struct rte_eth_fdir_filter *fdir_filter, + union ixgbe_atr_input *input); +static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, + uint32_t key); +static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input, + enum rte_fdir_pballoc_type pballoc); +static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, + enum rte_fdir_pballoc_type pballoc); +static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, + union ixgbe_atr_input *input, uint8_t queue, + uint32_t fdircmd, uint32_t fdirhash); +static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw, + union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd, + uint32_t fdirhash); +static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev, + const struct rte_eth_fdir_filter *fdir_filter, + bool del, + bool update); /** * This function is based on ixgbe_fdir_enable_82599() in ixgbe/ixgbe_82599.c. * It adds extra configuration of fdirctrl that is common for all filter types. @@ -214,6 +235,215 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev) return 0; } +/** + * Reverse the bits in FDIR registers that store 2 x 16 bit masks. + * + * @hi_dword: Bits 31:16 mask to be bit swapped. + * @lo_dword: Bits 15:0 mask to be bit swapped. + * + * Flow director uses several registers to store 2 x 16 bit masks with the + * bits reversed such as FDIRTCPM, FDIRUDPM and FDIRIP6M. The LS bit of the + * mask affects the MS bit/byte of the target. This function reverses the + * bits in these masks. + * **/ +static uint32_t +reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword) +{ + u32 mask = hi_dword << 16; + mask |= lo_dword; + mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); + mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); + mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); + return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); +} + +/* + * This macro exists in ixgbe/ixgbe_82599.c, however in that file it reverses + * the bytes, and then reverses them again. So here it does nothing. + */ +#define IXGBE_WRITE_REG_BE32 IXGBE_WRITE_REG + +/* + * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c, + * but makes use of the rte_fdir_masks structure to see which bits to set. + */ +static int +fdir_set_input_mask_82599(struct ixgbe_hw *hw, + struct rte_fdir_masks *input_mask) +{ + /* mask VM pool since it is currently not supported */ + u32 fdirm = IXGBE_FDIRM_POOL; + u32 fdirtcpm; /* TCP source and destination port masks. */ + u32 fdiripv6m; /* IPv6 source and destination masks. */ + + PMD_INIT_FUNC_TRACE(); + + /* + * Program the relevant mask registers. If src/dst_port or src/dst_addr + * are zero, then assume a full mask for that field. Also assume that + * a VLAN of 0 is unspecified, so mask that out as well. L4type + * cannot be masked out in this implementation. + */ + if (input_mask->only_ip_flow) { + /* use the L4 protocol mask for raw IPv4/IPv6 traffic */ + fdirm |= IXGBE_FDIRM_L4P; + if (input_mask->dst_port_mask || input_mask->src_port_mask) { + PMD_INIT_LOG(ERR, " Error on src/dst port mask"); + return -EINVAL; + } + } + + if (!input_mask->comp_ipv6_dst) + /* mask DIPV6 */ + fdirm |= IXGBE_FDIRM_DIPv6; + + if (!input_mask->vlan_id) + /* mask VLAN ID*/ + fdirm |= IXGBE_FDIRM_VLANID; + + if (!input_mask->vlan_prio) + /* mask VLAN priority */ + fdirm |= IXGBE_FDIRM_VLANP; + + if (!input_mask->flexbytes) + /* Mask Flex Bytes */ + fdirm |= IXGBE_FDIRM_FLEX; + + IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); + + /* store the TCP/UDP port masks, bit reversed from port layout */ + fdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask, + input_mask->src_port_mask); + + /* write both the same so that UDP and TCP use the same mask */ + IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); + IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); + + if (!input_mask->set_ipv6_mask) { + /* Store source and destination IPv4 masks (big-endian) */ + IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, + IXGBE_NTOHL(~input_mask->src_ipv4_mask)); + IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, + IXGBE_NTOHL(~input_mask->dst_ipv4_mask)); + } else { + /* Store source and destination IPv6 masks (bit reversed) */ + fdiripv6m = reverse_fdir_bitmasks(input_mask->dst_ipv6_mask, + input_mask->src_ipv6_mask); + + IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m); + } + + return IXGBE_SUCCESS; +} + +int +ixgbe_fdir_set_masks(struct rte_eth_dev *dev, struct rte_fdir_masks *fdir_masks) +{ + struct ixgbe_hw *hw; + int err; + + PMD_INIT_FUNC_TRACE(); + + hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->mac.type != ixgbe_mac_82599EB && + hw->mac.type != ixgbe_mac_X540 && + hw->mac.type != ixgbe_mac_X550 && + hw->mac.type != ixgbe_mac_X550EM_x) + return -ENOSYS; + + err = ixgbe_reinit_fdir_tables_82599(hw); + if (err) { + PMD_INIT_LOG(ERR, "reinit of fdir tables failed"); + return -EIO; + } + + return fdir_set_input_mask_82599(hw, fdir_masks); +} + +/* + * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used + * by the IXGBE driver code. + */ +static int +ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter, + union ixgbe_atr_input *input) +{ + input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci; + input->formatted.flex_bytes = (uint16_t)( + (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) | + (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF)); + + switch (fdir_filter->input.flow_type) { + case RTE_ETH_FLOW_TYPE_UDPV4: + input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; + break; + case RTE_ETH_FLOW_TYPE_TCPV4: + input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; + break; + case RTE_ETH_FLOW_TYPE_SCTPV4: + input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; + break; + case RTE_ETH_FLOW_TYPE_IPV4_OTHER: + input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; + break; + case RTE_ETH_FLOW_TYPE_UDPV6: + input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6; + break; + case RTE_ETH_FLOW_TYPE_TCPV6: + input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; + break; + case RTE_ETH_FLOW_TYPE_SCTPV6: + input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6; + break; + case RTE_ETH_FLOW_TYPE_IPV6_OTHER: + input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6; + break; + default: + PMD_DRV_LOG(ERR, " Error on flow_type input"); + return -EINVAL; + } + + switch (fdir_filter->input.flow_type) { + case RTE_ETH_FLOW_TYPE_UDPV4: + case RTE_ETH_FLOW_TYPE_TCPV4: + input->formatted.src_port = + fdir_filter->input.flow.udp4_flow.src_port; + input->formatted.dst_port = + fdir_filter->input.flow.udp4_flow.dst_port; + /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/ + case RTE_ETH_FLOW_TYPE_SCTPV4: + case RTE_ETH_FLOW_TYPE_IPV4_OTHER: + input->formatted.src_ip[0] = + fdir_filter->input.flow.ip4_flow.src_ip; + input->formatted.dst_ip[0] = + fdir_filter->input.flow.ip4_flow.dst_ip; + break; + + case RTE_ETH_FLOW_TYPE_UDPV6: + case RTE_ETH_FLOW_TYPE_TCPV6: + input->formatted.src_port = + fdir_filter->input.flow.udp6_flow.src_port; + input->formatted.dst_port = + fdir_filter->input.flow.udp6_flow.dst_port; + /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/ + case RTE_ETH_FLOW_TYPE_SCTPV6: + case RTE_ETH_FLOW_TYPE_IPV6_OTHER: + rte_memcpy(input->formatted.src_ip, + fdir_filter->input.flow.ipv6_flow.src_ip, + sizeof(input->formatted.src_ip)); + rte_memcpy(input->formatted.dst_ip, + fdir_filter->input.flow.ipv6_flow.dst_ip, + sizeof(input->formatted.dst_ip)); + break; + default: + PMD_DRV_LOG(ERR, " Error on flow_type input"); + return -EINVAL; + } + + return 0; +} + /* * The below function is taken from the FreeBSD IXGBE drivers release * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK @@ -230,9 +460,9 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev) * @stream: input bitstream to compute the hash on * @key: 32-bit hash key **/ -static u32 +static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, - u32 key) + uint32_t key) { /* * The algorithm is as follows: @@ -315,6 +545,43 @@ ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, return hash_result; } +static uint32_t +atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, + enum rte_fdir_pballoc_type pballoc) +{ + if (pballoc == RTE_FDIR_PBALLOC_256K) + return ixgbe_atr_compute_hash_82599(input, + IXGBE_ATR_BUCKET_HASH_KEY) & + PERFECT_BUCKET_256KB_HASH_MASK; + else if (pballoc == RTE_FDIR_PBALLOC_128K) + return ixgbe_atr_compute_hash_82599(input, + IXGBE_ATR_BUCKET_HASH_KEY) & + PERFECT_BUCKET_128KB_HASH_MASK; + else + return ixgbe_atr_compute_hash_82599(input, + IXGBE_ATR_BUCKET_HASH_KEY) & + PERFECT_BUCKET_64KB_HASH_MASK; +} + +/** + * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete + * @hw: pointer to hardware structure + */ +static inline int +ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd) +{ + int i; + + for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { + *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); + if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) + return 0; + rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US); + } + + return -ETIMEDOUT; +} + /* * Calculate the hash value needed for signature-match filters. In the FreeBSD * driver, this is done by the optimised function @@ -346,6 +613,63 @@ atr_compute_sig_hash_82599(union ixgbe_atr_input *input, return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash; } +/* + * This is based on ixgbe_fdir_write_perfect_filter_82599() in + * ixgbe/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register + * added, and IPv6 support also added. The hash value is also pre-calculated + * as the pballoc value is needed to do it. + */ +static int +fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, + union ixgbe_atr_input *input, uint8_t queue, + uint32_t fdircmd, uint32_t fdirhash) +{ + uint32_t fdirport, fdirvlan; + int err = 0; + + /* record the IPv4 address (big-endian) */ + IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); + IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); + + /* record source and destination port (little-endian)*/ + fdirport = IXGBE_NTOHS(input->formatted.dst_port); + fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; + fdirport |= IXGBE_NTOHS(input->formatted.src_port); + IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); + + /* record vlan (little-endian) and flex_bytes(big-endian) */ + fdirvlan = input->formatted.flex_bytes; + fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; + fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); + IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); + + /* configure FDIRHASH register */ + IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); + + /* + * flush all previous writes to make certain registers are + * programmed prior to issuing the command + */ + IXGBE_WRITE_FLUSH(hw); + + /* configure FDIRCMD register */ + fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW | + IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; + fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; + fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; + fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; + + IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); + + PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash); + + err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); + if (err < 0) + PMD_DRV_LOG(ERR, "Timeout writing flow director filter."); + + return err; +} + /** * This function is based on ixgbe_atr_add_signature_filter_82599() in * ixgbe/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports @@ -361,12 +685,12 @@ atr_compute_sig_hash_82599(union ixgbe_atr_input *input, * @fdircmd: any extra flags to set in fdircmd register * @fdirhash: pre-calculated hash value for the filter **/ -static void +static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw, - union ixgbe_atr_input *input, u8 queue, u32 fdircmd, - u32 fdirhash) + union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd, + uint32_t fdirhash) { - u64 fdirhashcmd; + int err = 0; PMD_INIT_FUNC_TRACE(); @@ -374,164 +698,43 @@ fdir_add_signature_filter_82599(struct ixgbe_hw *hw, fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; - fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; + fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; - /* - * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits - * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. - */ - fdirhashcmd = (u64)fdircmd << 32; - fdirhashcmd |= fdirhash; - IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); + IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); + IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); + + PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash); - PMD_INIT_LOG(DEBUG, "Tx Queue=%x hash=%x", queue, (u32)fdirhashcmd); + err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); + if (err < 0) + PMD_DRV_LOG(ERR, "Timeout writing flow director filter."); + + return err; } /* - * Convert DPDK rte_fdir_filter struct to ixgbe_atr_input union that is used - * by the IXGBE driver code. + * This is based on ixgbe_fdir_erase_perfect_filter_82599() in + * ixgbe/ixgbe_82599.c. It is modified to take in the hash as a parameter so + * that it can be used for removing signature and perfect filters. */ static int -fdir_filter_to_atr_input(struct rte_fdir_filter *fdir_filter, - union ixgbe_atr_input *input) +fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash) { - if ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP || - fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE) && - (fdir_filter->port_src || fdir_filter->port_dst)) { - PMD_INIT_LOG(ERR, "Invalid fdir_filter"); - return -EINVAL; - } + uint32_t fdircmd = 0; + int err = 0; - memset(input, 0, sizeof(*input)); + IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); - input->formatted.vlan_id = fdir_filter->vlan_id; - input->formatted.src_port = fdir_filter->port_src; - input->formatted.dst_port = fdir_filter->port_dst; - input->formatted.flex_bytes = fdir_filter->flex_bytes; - - switch (fdir_filter->l4type) { - case RTE_FDIR_L4TYPE_TCP: - input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; - break; - case RTE_FDIR_L4TYPE_UDP: - input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; - break; - case RTE_FDIR_L4TYPE_SCTP: - input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; - break; - case RTE_FDIR_L4TYPE_NONE: - input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; - break; - default: - PMD_INIT_LOG(ERR, " Error on l4type input"); - return -EINVAL; - } - - if (fdir_filter->iptype == RTE_FDIR_IPTYPE_IPV6) { - input->formatted.flow_type |= IXGBE_ATR_L4TYPE_IPV6_MASK; - - input->formatted.src_ip[0] = fdir_filter->ip_src.ipv6_addr[0]; - input->formatted.src_ip[1] = fdir_filter->ip_src.ipv6_addr[1]; - input->formatted.src_ip[2] = fdir_filter->ip_src.ipv6_addr[2]; - input->formatted.src_ip[3] = fdir_filter->ip_src.ipv6_addr[3]; - - input->formatted.dst_ip[0] = fdir_filter->ip_dst.ipv6_addr[0]; - input->formatted.dst_ip[1] = fdir_filter->ip_dst.ipv6_addr[1]; - input->formatted.dst_ip[2] = fdir_filter->ip_dst.ipv6_addr[2]; - input->formatted.dst_ip[3] = fdir_filter->ip_dst.ipv6_addr[3]; - - } else { - input->formatted.src_ip[0] = fdir_filter->ip_src.ipv4_addr; - input->formatted.dst_ip[0] = fdir_filter->ip_dst.ipv4_addr; - } - - return 0; -} - -/* - * Adds or updates a signature filter. - * - * dev: ethernet device to add filter to - * fdir_filter: filter details - * queue: queue index to direct traffic to - * update: 0 to add a new filter, otherwise update existing. - */ -static int -fdir_add_update_signature_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint8_t queue, int update) -{ - struct ixgbe_hw *hw= IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0; - uint32_t fdirhash; - union ixgbe_atr_input input; - int err; - - if (hw->mac.type != ixgbe_mac_82599EB && - hw->mac.type != ixgbe_mac_X540 && - hw->mac.type != ixgbe_mac_X550 && - hw->mac.type != ixgbe_mac_X550EM_x) - return -ENOSYS; - - err = fdir_filter_to_atr_input(fdir_filter, &input); - if (err) - return err; - - fdirhash = atr_compute_sig_hash_82599(&input, - dev->data->dev_conf.fdir_conf.pballoc); - fdir_add_signature_filter_82599(hw, &input, queue, fdircmd_flags, - fdirhash); - return 0; -} - -int -ixgbe_fdir_add_signature_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint8_t queue) -{ - PMD_INIT_FUNC_TRACE(); - return fdir_add_update_signature_filter(dev, fdir_filter, queue, 0); -} - -int -ixgbe_fdir_update_signature_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint8_t queue) -{ - PMD_INIT_FUNC_TRACE(); - return fdir_add_update_signature_filter(dev, fdir_filter, queue, 1); -} - -/* - * This is based on ixgbe_fdir_erase_perfect_filter_82599() in - * ixgbe/ixgbe_82599.c. It is modified to take in the hash as a parameter so - * that it can be used for removing signature and perfect filters. - */ -static s32 -fdir_erase_filter_82599(struct ixgbe_hw *hw, - __rte_unused union ixgbe_atr_input *input, uint32_t fdirhash) -{ - u32 fdircmd = 0; - u32 retry_count; - s32 err = 0; - - IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); - - /* flush hash to HW */ - IXGBE_WRITE_FLUSH(hw); + /* flush hash to HW */ + IXGBE_WRITE_FLUSH(hw); /* Query if filter is present */ IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); - for (retry_count = 10; retry_count; retry_count--) { - /* allow 10us for query to process */ - usec_delay(10); - /* verify query completed successfully */ - fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); - if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK)) - break; - } - - if (!retry_count) { - PMD_INIT_LOG(ERR, "Timeout querying for flow director filter"); - err = -EIO; + err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); + if (err < 0) { + PMD_INIT_LOG(ERR, "Timeout querying for flow director filter."); + return err; } /* if filter exists in hardware then remove it */ @@ -541,331 +744,97 @@ fdir_erase_filter_82599(struct ixgbe_hw *hw, IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_REMOVE_FLOW); } - + err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); + if (err < 0) + PMD_INIT_LOG(ERR, "Timeout erasing flow director filter."); return err; -} - -int -ixgbe_fdir_remove_signature_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter) -{ - struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - union ixgbe_atr_input input; - int err; - PMD_INIT_FUNC_TRACE(); - - if (hw->mac.type != ixgbe_mac_82599EB && - hw->mac.type != ixgbe_mac_X540 && - hw->mac.type != ixgbe_mac_X550 && - hw->mac.type != ixgbe_mac_X550EM_x) - return -ENOSYS; - - err = fdir_filter_to_atr_input(fdir_filter, &input); - if (err) - return err; - - return fdir_erase_filter_82599(hw, &input, - atr_compute_sig_hash_82599(&input, - dev->data->dev_conf.fdir_conf.pballoc)); -} - -/** - * Reverse the bits in FDIR registers that store 2 x 16 bit masks. - * - * @hi_dword: Bits 31:16 mask to be bit swapped. - * @lo_dword: Bits 15:0 mask to be bit swapped. - * - * Flow director uses several registers to store 2 x 16 bit masks with the - * bits reversed such as FDIRTCPM, FDIRUDPM and FDIRIP6M. The LS bit of the - * mask affects the MS bit/byte of the target. This function reverses the - * bits in these masks. - * **/ -static uint32_t -reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword) -{ - u32 mask = hi_dword << 16; - mask |= lo_dword; - mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); - mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); - mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); - return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); } /* - * This macro exists in ixgbe/ixgbe_82599.c, however in that file it reverses - * the bytes, and then reverses them again. So here it does nothing. - */ -#define IXGBE_WRITE_REG_BE32 IXGBE_WRITE_REG - -/* - * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c, - * but makes use of the rte_fdir_masks structure to see which bits to set. + * ixgbe_add_del_fdir_filter - add or remove a flow diretor filter. + * @dev: pointer to the structure rte_eth_dev + * @fdir_filter: fdir filter entry + * @del: 1 - delete, 0 - add + * @update: 1 - update */ static int -fdir_set_input_mask_82599(struct ixgbe_hw *hw, - struct rte_fdir_masks *input_mask) -{ - /* mask VM pool since it is currently not supported */ - u32 fdirm = IXGBE_FDIRM_POOL; - u32 fdirtcpm; /* TCP source and destination port masks. */ - u32 fdiripv6m; /* IPv6 source and destination masks. */ - - PMD_INIT_FUNC_TRACE(); - - /* - * Program the relevant mask registers. If src/dst_port or src/dst_addr - * are zero, then assume a full mask for that field. Also assume that - * a VLAN of 0 is unspecified, so mask that out as well. L4type - * cannot be masked out in this implementation. - */ - if (input_mask->only_ip_flow) { - /* use the L4 protocol mask for raw IPv4/IPv6 traffic */ - fdirm |= IXGBE_FDIRM_L4P; - if (input_mask->dst_port_mask || input_mask->src_port_mask) { - PMD_INIT_LOG(ERR, " Error on src/dst port mask"); - return -EINVAL; - } - } - - if (!input_mask->comp_ipv6_dst) - /* mask DIPV6 */ - fdirm |= IXGBE_FDIRM_DIPv6; - - if (!input_mask->vlan_id) - /* mask VLAN ID*/ - fdirm |= IXGBE_FDIRM_VLANID; - - if (!input_mask->vlan_prio) - /* mask VLAN priority */ - fdirm |= IXGBE_FDIRM_VLANP; - - if (!input_mask->flexbytes) - /* Mask Flex Bytes */ - fdirm |= IXGBE_FDIRM_FLEX; - - IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); - - /* store the TCP/UDP port masks, bit reversed from port layout */ - fdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask, - input_mask->src_port_mask); - - /* write both the same so that UDP and TCP use the same mask */ - IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); - IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); - - if (!input_mask->set_ipv6_mask) { - /* Store source and destination IPv4 masks (big-endian) */ - IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, - IXGBE_NTOHL(~input_mask->src_ipv4_mask)); - IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, - IXGBE_NTOHL(~input_mask->dst_ipv4_mask)); - } - else { - /* Store source and destination IPv6 masks (bit reversed) */ - fdiripv6m = reverse_fdir_bitmasks(input_mask->dst_ipv6_mask, - input_mask->src_ipv6_mask); - - IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m); - } - - return IXGBE_SUCCESS; -} - -int -ixgbe_fdir_set_masks(struct rte_eth_dev *dev, struct rte_fdir_masks *fdir_masks) -{ - struct ixgbe_hw *hw; - int err; - - PMD_INIT_FUNC_TRACE(); - - hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - - if (hw->mac.type != ixgbe_mac_82599EB && - hw->mac.type != ixgbe_mac_X540 && - hw->mac.type != ixgbe_mac_X550 && - hw->mac.type != ixgbe_mac_X550EM_x) - return -ENOSYS; - - err = ixgbe_reinit_fdir_tables_82599(hw); - if (err) { - PMD_INIT_LOG(ERR, "reinit of fdir tables failed"); - return -EIO; - } - - return fdir_set_input_mask_82599(hw, fdir_masks); -} - -static uint32_t -atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, - enum rte_fdir_pballoc_type pballoc) -{ - if (pballoc == RTE_FDIR_PBALLOC_256K) - return ixgbe_atr_compute_hash_82599(input, - IXGBE_ATR_BUCKET_HASH_KEY) & - PERFECT_BUCKET_256KB_HASH_MASK; - else if (pballoc == RTE_FDIR_PBALLOC_128K) - return ixgbe_atr_compute_hash_82599(input, - IXGBE_ATR_BUCKET_HASH_KEY) & - PERFECT_BUCKET_128KB_HASH_MASK; - else - return ixgbe_atr_compute_hash_82599(input, - IXGBE_ATR_BUCKET_HASH_KEY) & - PERFECT_BUCKET_64KB_HASH_MASK; -} - -/* - * This is based on ixgbe_fdir_write_perfect_filter_82599() in - * ixgbe/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register - * added, and IPv6 support also added. The hash value is also pre-calculated - * as the pballoc value is needed to do it. - */ -static void -fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, union ixgbe_atr_input *input, - uint16_t soft_id, uint8_t queue, uint32_t fdircmd, - uint32_t fdirhash) -{ - u32 fdirport, fdirvlan; - - /* record the source address (big-endian) */ - if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) { - IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), input->formatted.src_ip[0]); - IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), input->formatted.src_ip[1]); - IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.src_ip[2]); - IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[3]); - } - else { - IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); - } - - /* record the first 32 bits of the destination address (big-endian) */ - IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); - - /* record source and destination port (little-endian)*/ - fdirport = IXGBE_NTOHS(input->formatted.dst_port); - fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; - fdirport |= IXGBE_NTOHS(input->formatted.src_port); - IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); - - /* record vlan (little-endian) and flex_bytes(big-endian) */ - fdirvlan = input->formatted.flex_bytes; - fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; - fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); - IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); - - /* configure FDIRHASH register */ - fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; - IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); - - /* - * flush all previous writes to make certain registers are - * programmed prior to issuing the command - */ - IXGBE_WRITE_FLUSH(hw); - - /* configure FDIRCMD register */ - fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW | - IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; - fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; - fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; - fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; - - IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); -} - -/* - * Adds or updates a perfect filter. - * - * dev: ethernet device to add filter to - * fdir_filter: filter details - * soft_id: software index for the filters - * queue: queue index to direct traffic to - * drop: non-zero if packets should be sent to the drop queue - * update: 0 to add a new filter, otherwise update existing. - */ -static int -fdir_add_update_perfect_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint16_t soft_id, - uint8_t queue, int drop, int update) +ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev, + const struct rte_eth_fdir_filter *fdir_filter, + bool del, + bool update) { struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0; + uint32_t fdircmd_flags; uint32_t fdirhash; union ixgbe_atr_input input; + uint8_t queue; + bool is_perfect = FALSE; int err; - if (hw->mac.type != ixgbe_mac_82599EB && - hw->mac.type != ixgbe_mac_X540 && - hw->mac.type != ixgbe_mac_X550 && - hw->mac.type != ixgbe_mac_X550EM_x) - return -ENOSYS; - - err = fdir_filter_to_atr_input(fdir_filter, &input); - if (err) - return err; - - if (drop) { - queue = dev->data->dev_conf.fdir_conf.drop_queue; - fdircmd_flags |= IXGBE_FDIRCMD_DROP; - } - - fdirhash = atr_compute_perfect_hash_82599(&input, - dev->data->dev_conf.fdir_conf.pballoc); + if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_NONE) + return -ENOTSUP; - fdir_write_perfect_filter_82599(hw, &input, soft_id, queue, - fdircmd_flags, fdirhash); - return 0; -} + if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) + is_perfect = TRUE; -int -ixgbe_fdir_add_perfect_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint16_t soft_id, - uint8_t queue, uint8_t drop) -{ - PMD_INIT_FUNC_TRACE(); - return fdir_add_update_perfect_filter(dev, fdir_filter, soft_id, queue, - drop, 0); -} - -int -ixgbe_fdir_update_perfect_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, uint16_t soft_id, - uint8_t queue, uint8_t drop) -{ - PMD_INIT_FUNC_TRACE(); - return fdir_add_update_perfect_filter(dev, fdir_filter, soft_id, queue, - drop, 1); -} - -int -ixgbe_fdir_remove_perfect_filter(struct rte_eth_dev *dev, - struct rte_fdir_filter *fdir_filter, - uint16_t soft_id) -{ - struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - union ixgbe_atr_input input; - uint32_t fdirhash; - int err; - - PMD_INIT_FUNC_TRACE(); + memset(&input, 0, sizeof(input)); - if (hw->mac.type != ixgbe_mac_82599EB && - hw->mac.type != ixgbe_mac_X540 && - hw->mac.type != ixgbe_mac_X550 && - hw->mac.type != ixgbe_mac_X550EM_x) - return -ENOSYS; - - err = fdir_filter_to_atr_input(fdir_filter, &input); + err = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input); if (err) return err; - /* configure FDIRHASH register */ - fdirhash = atr_compute_perfect_hash_82599(&input, - dev->data->dev_conf.fdir_conf.pballoc); - fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; + if (is_perfect) { + if (input.formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) { + PMD_DRV_LOG(ERR, "IPv6 is not supported in" + " perfect mode!"); + return -ENOTSUP; + } + fdirhash = atr_compute_perfect_hash_82599(&input, + dev->data->dev_conf.fdir_conf.pballoc); + fdirhash |= fdir_filter->soft_id << + IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; + } else + fdirhash = atr_compute_sig_hash_82599(&input, + dev->data->dev_conf.fdir_conf.pballoc); + + if (del) { + err = fdir_erase_filter_82599(hw, fdirhash); + if (err < 0) + PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!"); + else + PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!"); + return err; + } + /* add or update an fdir filter*/ + fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0; + if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT) { + if (is_perfect) { + queue = dev->data->dev_conf.fdir_conf.drop_queue; + fdircmd_flags |= IXGBE_FDIRCMD_DROP; + } else { + PMD_DRV_LOG(ERR, "Drop option is not supported in" + " signature mode."); + return -EINVAL; + } + } else if (fdir_filter->action.rx_queue < IXGBE_MAX_RX_QUEUE_NUM) + queue = (uint8_t)fdir_filter->action.rx_queue; + else + return -EINVAL; + + if (is_perfect) { + err = fdir_write_perfect_filter_82599(hw, &input, queue, + fdircmd_flags, fdirhash); + } else { + err = fdir_add_signature_filter_82599(hw, &input, queue, + fdircmd_flags, fdirhash); + } + if (err < 0) + PMD_DRV_LOG(ERR, "Fail to add FDIR filter!"); + else + PMD_DRV_LOG(DEBUG, "Success to add FDIR filter"); - return fdir_erase_filter_82599(hw, &input, fdirhash); + return err; } void @@ -917,3 +886,49 @@ ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir *fdir) fdir->f_remove = info->f_remove; fdir->f_add = info->f_add; } + +/* + * ixgbe_fdir_ctrl_func - deal with all operations on flow director. + * @dev: pointer to the structure rte_eth_dev + * @filter_op:operation will be taken + * @arg: a pointer to specific structure corresponding to the filter_op + */ +int +ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev, + enum rte_filter_op filter_op, void *arg) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int ret = 0; + + if (hw->mac.type != ixgbe_mac_82599EB && + hw->mac.type != ixgbe_mac_X540 && + hw->mac.type != ixgbe_mac_X550 && + hw->mac.type != ixgbe_mac_X550EM_x) + return -ENOTSUP; + + if (filter_op == RTE_ETH_FILTER_NOP) + return 0; + + if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) + return -EINVAL; + + switch (filter_op) { + case RTE_ETH_FILTER_ADD: + ret = ixgbe_add_del_fdir_filter(dev, + (struct rte_eth_fdir_filter *)arg, FALSE, FALSE); + break; + case RTE_ETH_FILTER_UPDATE: + ret = ixgbe_add_del_fdir_filter(dev, + (struct rte_eth_fdir_filter *)arg, FALSE, TRUE); + break; + case RTE_ETH_FILTER_DELETE: + ret = ixgbe_add_del_fdir_filter(dev, + (struct rte_eth_fdir_filter *)arg, TRUE, FALSE); + break; + default: + PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); + ret = -EINVAL; + break; + } + return ret; +} -- 1.9.3