From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 19CA6AD89 for ; Thu, 12 Feb 2015 13:02:15 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 12 Feb 2015 03:54:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,565,1418112000"; d="scan'208";a="453649862" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by FMSMGA003.fm.intel.com with ESMTP; 12 Feb 2015 03:47:13 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t1CC1rU4008164; Thu, 12 Feb 2015 20:01:53 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t1CC1n4Q030564; Thu, 12 Feb 2015 20:01:51 +0800 Received: (from couyang@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t1CC1nt0030560; Thu, 12 Feb 2015 20:01:49 +0800 From: Ouyang Changchun To: dev@dpdk.org Date: Thu, 12 Feb 2015 20:00:50 +0800 Message-Id: <1423742468-30404-19-git-send-email-changchun.ouyang@intel.com> X-Mailer: git-send-email 1.7.12.2 In-Reply-To: <1423742468-30404-1-git-send-email-changchun.ouyang@intel.com> References: <1423742468-30404-1-git-send-email-changchun.ouyang@intel.com> Subject: [dpdk-dev] [PATCH 18/36] ixgbe base codes: Restructure host interface command X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Feb 2015 12:02:16 -0000 Request and response command have different struct. Signed-off-by: Changchun Ouyang --- lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h | 22 ++++++++++++++++----- lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c | 34 ++++++++++++++++----------------- 2 files changed, 34 insertions(+), 22 deletions(-) diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h index 6043eac..8946006 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h @@ -2821,13 +2821,25 @@ struct ixgbe_hic_hdr { u8 checksum; }; -struct ixgbe_hic_hdr2 { +struct ixgbe_hic_hdr2_req { u8 cmd; - u8 buf_len1; - u8 buf_len2; + u8 buf_lenh; + u8 buf_lenl; u8 checksum; }; +struct ixgbe_hic_hdr2_rsp { + u8 cmd; + u8 buf_lenl; + u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ + u8 checksum; +}; + +union ixgbe_hic_hdr2 { + struct ixgbe_hic_hdr2_req req; + struct ixgbe_hic_hdr2_rsp rsp; +}; + struct ixgbe_hic_drv_info { struct ixgbe_hic_hdr hdr; u8 port_num; @@ -2841,7 +2853,7 @@ struct ixgbe_hic_drv_info { /* These need to be dword aligned */ struct ixgbe_hic_read_shadow_ram { - struct ixgbe_hic_hdr2 hdr; + union ixgbe_hic_hdr2 hdr; u32 address; u16 length; u16 pad2; @@ -2850,7 +2862,7 @@ struct ixgbe_hic_read_shadow_ram { }; struct ixgbe_hic_write_shadow_ram { - struct ixgbe_hic_hdr2 hdr; + union ixgbe_hic_hdr2 hdr; u32 address; u16 length; u16 pad2; diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c index e3d8fc1..d8a0c19 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c @@ -1450,10 +1450,10 @@ s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, struct ixgbe_hic_read_shadow_ram buffer; DEBUGFUNC("ixgbe_read_ee_hostif_data_X550"); - buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD; - buffer.hdr.buf_len1 = 0; - buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN; - buffer.hdr.checksum = FW_DEFAULT_CHECKSUM; + buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; + buffer.hdr.req.buf_lenh = 0; + buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; + buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; /* convert offset from words to bytes */ buffer.address = IXGBE_CPU_TO_BE32(offset * 2); @@ -1531,10 +1531,10 @@ s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, else words_to_read = words; - buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD; - buffer.hdr.buf_len1 = 0; - buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN; - buffer.hdr.checksum = FW_DEFAULT_CHECKSUM; + buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; + buffer.hdr.req.buf_lenh = 0; + buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; + buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; /* convert offset from words to bytes */ buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); @@ -1588,10 +1588,10 @@ s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); - buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD; - buffer.hdr.buf_len1 = 0; - buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN; - buffer.hdr.checksum = FW_DEFAULT_CHECKSUM; + buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; + buffer.hdr.req.buf_lenh = 0; + buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; + buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; /* one word */ buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); @@ -1905,14 +1905,14 @@ s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) { s32 status = IXGBE_SUCCESS; - struct ixgbe_hic_hdr2 buffer; + union ixgbe_hic_hdr2 buffer; DEBUGFUNC("ixgbe_update_flash_X550"); - buffer.cmd = FW_SHADOW_RAM_DUMP_CMD; - buffer.buf_len1 = 0; - buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN; - buffer.checksum = FW_DEFAULT_CHECKSUM; + buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; + buffer.req.buf_lenh = 0; + buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; + buffer.req.checksum = FW_DEFAULT_CHECKSUM; status = ixgbe_host_interface_command(hw, (u32 *)&buffer, sizeof(buffer), -- 1.8.4.2