From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id D9A2F9A92 for ; Wed, 10 Jun 2015 17:11:46 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP; 10 Jun 2015 08:10:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,588,1427785200"; d="scan'208";a="744343667" Received: from ajyongmo-mobl1.amr.corp.intel.com (HELO lwang14-MOBL6.amr.corp.intel.com) ([10.254.232.55]) by orsmga002.jf.intel.com with ESMTP; 10 Jun 2015 08:10:05 -0700 From: Liang-Min Larry Wang To: dev@dpdk.org Date: Wed, 10 Jun 2015 11:09:54 -0400 Message-Id: <1433948996-9716-3-git-send-email-liang-min.wang@intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1433948996-9716-1-git-send-email-liang-min.wang@intel.com> References: <1432946276-9424-1-git-send-email-liang-min.wang@intel.com> <1433948996-9716-1-git-send-email-liang-min.wang@intel.com> Cc: Liang-Min Larry Wang Subject: [dpdk-dev] [PATCH v4 2/4] ixgbe: add ops to support ethtool ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Jun 2015 15:11:48 -0000 add function to support ethtool ops: - set_mac_addr - get_ringparam - get_reg_length - get_regs - get_eeprom_length - get_eeprom - set_eeprom Signed-off-by: Liang-Min Larry Wang --- drivers/net/ixgbe/ixgbe_ethdev.c | 207 +++++++++++++++++++++++ drivers/net/ixgbe/ixgbe_regs.h | 357 +++++++++++++++++++++++++++++++++++++++ drivers/net/ixgbe/ixgbe_rxtx.c | 16 ++ drivers/net/ixgbe/ixgbe_rxtx.h | 1 + 4 files changed, 581 insertions(+) create mode 100644 drivers/net/ixgbe/ixgbe_regs.h diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 0d9f9b2..f3b80a8 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -68,6 +68,9 @@ #include "ixgbe_ethdev.h" #include "ixgbe_bypass.h" #include "ixgbe_rxtx.h" +#include "base/ixgbe_type.h" +#include "base/ixgbe_phy.h" +#include "ixgbe_regs.h" /* * High threshold controlling when to start sending XOFF frames. Must be at @@ -91,6 +94,7 @@ #define IXGBE_MMW_SIZE_DEFAULT 0x4 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 +#define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ /* * Default values for RX/TX configuration @@ -179,6 +183,7 @@ static void ixgbe_dev_interrupt_delayed_handler(void *param); static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr, uint32_t index, uint32_t pool); static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); +static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr); static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config); /* For Virtual Function support */ @@ -223,6 +228,8 @@ static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr, uint32_t index, uint32_t pool); static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); +static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, + struct ether_addr *mac_addr); static int ixgbe_syn_filter_set(struct rte_eth_dev *dev, struct rte_eth_syn_filter *filter, bool add); @@ -257,6 +264,17 @@ static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, void *arg); static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); +/* Ethtool op support */ +static int ixgbe_get_ringparam(struct rte_eth_dev *dev, struct rte_dev_ring_info *param); +static int ixgbe_get_reg_length(struct rte_eth_dev *dev); +static int ixgbe_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs); +static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); +static int ixgbe_get_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom); +static int ixgbe_set_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom); + +static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); +static int ixgbevf_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs); + /* * Define VF Stats MACRO for Non "cleared on read" register */ @@ -355,6 +373,7 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = { .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, .mac_addr_add = ixgbe_add_rar, .mac_addr_remove = ixgbe_remove_rar, + .mac_addr_set = ixgbe_set_default_mac_addr, .uc_hash_table_set = ixgbe_uc_hash_table_set, .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, .mirror_rule_set = ixgbe_mirror_rule_set, @@ -381,6 +400,12 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = { .rss_hash_update = ixgbe_dev_rss_hash_update, .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, .filter_ctrl = ixgbe_dev_filter_ctrl, + .get_ringparam = ixgbe_get_ringparam, + .get_reg_length = ixgbe_get_reg_length, + .get_reg = ixgbe_get_regs, + .get_eeprom_length = ixgbe_get_eeprom_length, + .get_eeprom = ixgbe_get_eeprom, + .set_eeprom = ixgbe_set_eeprom, }; /* @@ -406,6 +431,9 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops = { .tx_queue_release = ixgbe_dev_tx_queue_release, .mac_addr_add = ixgbevf_add_mac_addr, .mac_addr_remove = ixgbevf_remove_mac_addr, + .mac_addr_set = ixgbevf_set_default_mac_addr, + .get_reg_length = ixgbevf_get_reg_length, + .get_reg = ixgbevf_get_regs, }; /** @@ -2883,6 +2911,16 @@ ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) ixgbe_clear_rar(hw, index); } +static void +ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) +{ + ixgbe_remove_rar(dev, 0); + + ether_addr_copy(addr, &dev->data->mac_addrs[0]); + + ixgbe_add_rar(dev, addr, 0, 0); +} + static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) { @@ -3713,6 +3751,16 @@ ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) } } +static void +ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + ether_addr_copy(addr, &dev->data->mac_addrs[0]); + + hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); +} + #define MAC_TYPE_FILTER_SUP(type) do {\ if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\ (type) != ixgbe_mac_X550)\ @@ -4439,6 +4487,165 @@ ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, return ret; } +static int +ixgbe_get_ringparam(struct rte_eth_dev *dev, + struct rte_dev_ring_info *ring_param) +{ + /* Pending rx/tx descriptors in queue #0 */ + struct ixgbe_tx_queue *txq = dev->data->tx_queues[0]; + struct ixgbe_rx_queue *rxq = dev->data->rx_queues[0]; + + ring_param->rx_pending = rxq->nb_rx_desc - ixgbe_dev_rx_queue_count(dev, 0); + ring_param->tx_pending = txq->nb_tx_desc - ixgbe_dev_tx_queue_count(dev, 0); + /* The ixgbe descriptor ring is multiple of 8 descriptor, i.e. module by 8*16 bytes */ + ring_param->rx_max_pending = IXGBE_MAX_RING_DESC; + ring_param->tx_max_pending = IXGBE_MAX_RING_DESC; + + return 0; +} + +static int +ixgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int count = 0; + int g_ind = 0; + reg_info *reg_group; + reg_info **reg_set = + (hw->mac.type == ixgbe_mac_82598EB)?ixgbe_regs_mac_82598EB:ixgbe_regs_others; + + reg_group = reg_set[g_ind++]; + while(reg_group) { + count += ixgbe_regs_group_count(reg_group); + reg_group = reg_set[g_ind++]; + } + + return count; +} + +static int +ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) +{ + int count = 0; + int g_ind = 0; + reg_info *reg_group; + + reg_group = ixgbevf_regs[g_ind++]; + while(reg_group) { + count += ixgbe_regs_group_count(reg_group); + reg_group = ixgbevf_regs[g_ind++]; + } + + return count; +} + +static int +ixgbe_get_regs(struct rte_eth_dev *dev, + struct rte_dev_reg_info *regs) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t *regs_buff = regs->buf; + int g_ind = 0; + int count = 0; + reg_info *reg_group; + reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB)? + ixgbe_regs_mac_82598EB:ixgbe_regs_others; + + /* + * Support only full register dump + */ + if ((regs->leng == 0) || + (regs->leng == (uint32_t)ixgbe_get_reg_length(dev))) { + regs->version = hw->mac.type << 24 | hw->revision_id << 16 | + hw->device_id; + reg_group = reg_set[g_ind++]; + while(reg_group) { + count += ixgbe_read_regs_group(dev, ®s_buff[count], reg_group); + reg_group = reg_set[g_ind++]; + } + return 0; + } + + return -ENOTSUP; +} + +static int +ixgbevf_get_regs(struct rte_eth_dev *dev, + struct rte_dev_reg_info *regs) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t *regs_buff = regs->buf; + int g_ind = 0; + int count = 0; + reg_info *reg_group; + + /* + * Support only full register dump + */ + if ((regs->leng == 0) || + (regs->leng == (uint32_t)ixgbevf_get_reg_length(dev))) { + regs->version = hw->mac.type << 24 | hw->revision_id << 16 | + hw->device_id; + reg_group = ixgbevf_regs[g_ind++]; + while(reg_group) { + count += ixgbe_read_regs_group(dev, ®s_buff[count], reg_group); + reg_group = ixgbevf_regs[g_ind++]; + } + return 0; + } + + return -ENOTSUP; +} + +static int +ixgbe_get_eeprom_length(struct rte_eth_dev *dev) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + /* Return unit is byte count */ + return hw->eeprom.word_size*2; +} + +static int +ixgbe_get_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *in_eeprom) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ixgbe_eeprom_info *eeprom = &hw->eeprom; + uint16_t *data = in_eeprom->buf; + int first, leng; + + first = in_eeprom->offset >> 1; + leng = in_eeprom->leng >> 1; + if ((first >= hw->eeprom.word_size) || + ((first+leng) >= hw->eeprom.word_size)) + return -EINVAL; + + in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); + + return eeprom->ops.read_buffer(hw, first, leng, data); +} + +static int +ixgbe_set_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *in_eeprom) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ixgbe_eeprom_info *eeprom = &hw->eeprom; + uint16_t *data = in_eeprom->buf; + int first, leng; + + first = in_eeprom->offset >> 1; + leng = in_eeprom->leng >> 1; + if ((first >= hw->eeprom.word_size) || + ((first+leng) >= hw->eeprom.word_size)) + return -EINVAL; + + in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); + + return eeprom->ops.write_buffer(hw, first, leng, data); +} + static struct rte_driver rte_ixgbe_driver = { .type = PMD_PDEV, .init = rte_ixgbe_pmd_init, diff --git a/drivers/net/ixgbe/ixgbe_regs.h b/drivers/net/ixgbe/ixgbe_regs.h new file mode 100644 index 0000000..7025ed8 --- /dev/null +++ b/drivers/net/ixgbe/ixgbe_regs.h @@ -0,0 +1,357 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2015 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _IXGBE_REGS_H_ +#define _IXGBE_REGS_H_ + +#include "ixgbe_ethdev.h" + +struct ixgbe_hw; +typedef struct _reg_info { + uint32_t base_addr; + uint32_t count; + uint32_t stride; + const char *name; +} reg_info; + +static reg_info ixgbe_regs_general[] = { + {IXGBE_CTRL, 1, 1, "IXGBE_CTRL"}, + {IXGBE_STATUS, 1, 1, "IXGBE_STATUS"}, + {IXGBE_CTRL_EXT, 1, 1, "IXGBE_CTRL_EXT"}, + {IXGBE_ESDP, 1, 1, "IXGBE_ESDP"}, + {IXGBE_EODSDP, 1, 1, "IXGBE_EODSDP"}, + {IXGBE_LEDCTL, 1, 1, "IXGBE_LEDCTL"}, + {IXGBE_FRTIMER, 1, 1, "IXGBE_FRTIMER"}, + {IXGBE_TCPTIMER, 1, 1, "IXGBE_TCPTIMER"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbevf_regs_general[] = { + {IXGBE_CTRL, 1, 1, "IXGBE_CTRL"}, + {IXGBE_STATUS, 1, 1, "IXGBE_STATUS"}, + {IXGBE_VFLINKS, 1, 1, "IXGBE_VFLINKS"}, + {IXGBE_FRTIMER, 1, 1, "IXGBE_FRTIMER"}, + {IXGBE_VFMAILBOX, 1, 1, "IXGBE_VFMAILBOX"}, + {IXGBE_VFMBMEM, 16, 4, "IXGBE_VFMBMEM"}, + {IXGBE_VFRXMEMWRAP, 1, 1, "IXGBE_VFRXMEMWRAP"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_nvm [] = { + {IXGBE_EEC, 1, 1, "IXGBE_EEC"}, + {IXGBE_EERD, 1, 1, "IXGBE_EERD"}, + {IXGBE_FLA, 1, 1, "IXGBE_FLA"}, + {IXGBE_EEMNGCTL, 1, 1, "IXGBE_EEMNGCTL"}, + {IXGBE_EEMNGDATA, 1, 1, "IXGBE_EEMNGDATA"}, + {IXGBE_FLMNGCTL, 1, 1, "IXGBE_FLMNGCTL"}, + {IXGBE_FLMNGDATA, 1, 1, "IXGBE_FLMNGDATA"}, + {IXGBE_FLMNGCNT, 1, 1, "IXGBE_FLMNGCNT"}, + {IXGBE_FLOP, 1, 1, "IXGBE_FLOP"}, + {IXGBE_GRC, 1, 1, "IXGBE_GRC"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_interrupt [] = { + {IXGBE_EICS, 1, 1, "IXGBE_EICS"}, + {IXGBE_EIMS, 1, 1, "IXGBE_EIMS"}, + {IXGBE_EIMC, 1, 1, "IXGBE_EIMC"}, + {IXGBE_EIAC, 1, 1, "IXGBE_EIAC"}, + {IXGBE_EIAM, 1, 1, "IXGBE_EIAM"}, + {IXGBE_EITR(0), 24, 4, "IXGBE_EITR"}, + {IXGBE_IVAR(0), 24, 4, "IXGBE_IVAR"}, + {IXGBE_MSIXT, 1, 1, "IXGBE_MSIXT"}, + {IXGBE_MSIXPBA, 1, 1, "IXGBE_MSIXPBA"}, + {IXGBE_PBACL(0), 1, 4, "IXGBE_PBACL"}, + {IXGBE_GPIE, 1, 1, ""}, + {0, 0, 0, ""} +}; + +static reg_info ixgbevf_regs_interrupt [] = { + {IXGBE_VTEICR, 1, 1, "IXGBE_VTEICR"}, + {IXGBE_VTEICS, 1, 1, "IXGBE_VTEICS"}, + {IXGBE_VTEIMS, 1, 1, "IXGBE_VTEIMS"}, + {IXGBE_VTEIMC, 1, 1, "IXGBE_VTEIMC"}, + {IXGBE_VTEIAM, 1, 1, "IXGBE_VTEIAM"}, + {IXGBE_VTEITR(0), 2, 4, "IXGBE_VTEITR"}, + {IXGBE_VTIVAR(0), 4, 4, "IXGBE_VTIVAR"}, + {IXGBE_VTIVAR_MISC, 1, 1, "IXGBE_VTIVAR_MISC"}, + {IXGBE_VTRSCINT(0), 2, 4, "IXGBE_VTRSCINT"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_fctl_mac_82598EB[] = { + {IXGBE_PFCTOP, 1, 1, ""}, + {IXGBE_FCTTV(0), 4, 4, ""}, + {IXGBE_FCRTV, 1, 1, ""}, + {IXGBE_TFCS, 1, 1, ""}, + {IXGBE_FCRTL(0), 8, 8, "IXGBE_FCRTL"}, + {IXGBE_FCRTH(0), 8, 8, "IXGBE_FCRTH"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_fctl_others[] = { + {IXGBE_PFCTOP, 1, 1, ""}, + {IXGBE_FCTTV(0), 4, 4, ""}, + {IXGBE_FCRTV, 1, 1, ""}, + {IXGBE_TFCS, 1, 1, ""}, + {IXGBE_FCRTL_82599(0), 8, 4, "IXGBE_FCRTL"}, + {IXGBE_FCRTH_82599(0), 8, 4, "IXGBE_FCRTH"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_rxdma[] = { + {IXGBE_RDBAL(0), 64, 0x40, "IXGBE_RDBAL"}, + {IXGBE_RDBAH(0), 64, 0x40, "IXGBE_RDBAH"}, + {IXGBE_RDLEN(0), 64, 0x40, "IXGBE_RDLEN"}, + {IXGBE_RDH(0), 64, 0x40, "IXGBE_RDH"}, + {IXGBE_RDT(0), 64, 0x40, "IXGBE_RDT"}, + {IXGBE_RXDCTL(0), 64, 0x40, "IXGBE_RXDCTL"}, + {IXGBE_SRRCTL(0), 16, 0x4, "IXGBE_SRRCTL"}, + {IXGBE_DCA_RXCTRL(0), 16, 4, "IXGBE_DCA_RXCTRL"}, + {IXGBE_RDRXCTL, 1, 1, "IXGBE_RDRXCTL"}, + {IXGBE_RXPBSIZE(0), 8, 4, "IXGBE_RXPBSIZE"}, + {IXGBE_RXCTRL, 1, 1, "IXGBE_RXCTRL"}, + {IXGBE_DROPEN, 1, 1, "IXGBE_DROPEN"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbevf_regs_rxdma[] = { + {IXGBE_RDBAL(0), 8, 0x40, "IXGBE_RDBAL"}, + {IXGBE_RDBAH(0), 8, 0x40, "IXGBE_RDBAH"}, + {IXGBE_RDLEN(0), 8, 0x40, "IXGBE_RDLEN"}, + {IXGBE_RDH(0), 8, 0x40, "IXGBE_RDH"}, + {IXGBE_RDT(0), 8, 0x40, "IXGBE_RDT"}, + {IXGBE_RXDCTL(0), 8, 0x40, "IXGBE_RXDCTL"}, + {IXGBE_SRRCTL(0), 8, 0x40, "IXGBE_SRRCTL"}, + {IXGBE_VFPSRTYPE, 1, 1, "IXGBE_VFPSRTYPE"}, + {IXGBE_VFRSCCTL(0), 8, 0x40, "IXGBE_VFRSCCTL"}, + {IXGBE_PVFDCA_RXCTRL(0), 8, 0x40, "IXGBE_PVFDCA_RXCTRL"}, + {IXGBE_PVFDCA_TXCTRL(0), 8, 0x40, "IXGBE_PVFDCA_TXCTRL"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_rx [] = { + {IXGBE_RXCSUM, 1, 1, "IXGBE_RXCSUM"}, + {IXGBE_RFCTL, 1, 1, "IXGBE_RFCTL"}, + {IXGBE_RAL(0), 16, 8, "IXGBE_RAL"}, + {IXGBE_RAH(0), 16, 8, "IXGBE_RAH"}, + {IXGBE_PSRTYPE(0), 1, 4, "IXGBE_PSRTYPE"}, + {IXGBE_FCTRL, 1, 1, "IXGBE_FCTRL"}, + {IXGBE_VLNCTRL, 1, 1, "IXGBE_VLNCTRL"}, + {IXGBE_MCSTCTRL, 1, 1, "IXGBE_MCSTCTRL"}, + {IXGBE_MRQC, 1, 1, "IXGBE_MRQC"}, + {IXGBE_VMD_CTL, 1, 1, "IXGBE_VMD_CTL"}, + {IXGBE_IMIR(0), 8, 4, "IXGBE_IMIR"}, + {IXGBE_IMIREXT(0), 8, 4, "IXGBE_IMIREXT"}, + {IXGBE_IMIRVP, 1, 1, "IXGBE_IMIRVP"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_tx [] = { + {IXGBE_TDBAL(0), 32, 0x40, "IXGBE_TDBAL"}, + {IXGBE_TDBAH(0), 32, 0x40, "IXGBE_TDBAH"}, + {IXGBE_TDLEN(0), 32, 0x40, "IXGBE_TDLEN"}, + {IXGBE_TDH(0), 32, 0x40, "IXGBE_TDH"}, + {IXGBE_TDT(0), 32, 0x40, "IXGBE_TDT"}, + {IXGBE_TXDCTL(0), 32, 0x40, "IXGBE_TXDCTL"}, + {IXGBE_TDWBAL(0), 32, 0x40, "IXGBE_TDWBAL"}, + {IXGBE_TDWBAH(0), 32, 0x40, "IXGBE_TDWBAH"}, + {IXGBE_DTXCTL, 1, 1, "IXGBE_DTXCTL"}, + {IXGBE_DCA_TXCTRL(0), 16, 4, "IXGBE_DCA_TXCTRL"}, + {IXGBE_TXPBSIZE(0), 8, 4, "IXGBE_TXPBSIZE"}, + {IXGBE_MNGTXMAP, 1, 1, "IXGBE_MNGTXMAP"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbevf_regs_tx [] = { + {IXGBE_TDBAL(0), 4, 0x40, "IXGBE_TDBAL"}, + {IXGBE_TDBAH(0), 4, 0x40, "IXGBE_TDBAH"}, + {IXGBE_TDLEN(0), 4, 0x40, "IXGBE_TDLEN"}, + {IXGBE_TDH(0), 4, 0x40, "IXGBE_TDH"}, + {IXGBE_TDT(0), 4, 0x40, "IXGBE_TDT"}, + {IXGBE_TXDCTL(0), 4, 0x40, "IXGBE_TXDCTL"}, + {IXGBE_TDWBAL(0), 4, 0x40, "IXGBE_TDWBAL"}, + {IXGBE_TDWBAH(0), 4, 0x40, "IXGBE_TDWBAH"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_wakeup [] = { + {IXGBE_WUC, 1, 1, "IXGBE_WUC"}, + {IXGBE_WUFC, 1, 1, "IXGBE_WUFC"}, + {IXGBE_WUS, 1, 1, "IXGBE_WUS"}, + {IXGBE_IPAV, 1, 1, "IXGBE_IPAV"}, + {IXGBE_IP4AT, 1, 1, "IXGBE_IP4AT"}, + {IXGBE_IP6AT, 1, 1, "IXGBE_IP6AT"}, + {IXGBE_WUPL, 1, 1, "IXGBE_WUPL"}, + {IXGBE_WUPM, 1, 1, "IXGBE_WUPM"}, + {IXGBE_FHFT(0), 1, 1, "IXGBE_FHFT"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_dcb [] = { + {IXGBE_RMCS, 1, 1, "IXGBE_RMCS"}, + {IXGBE_DPMCS, 1, 1, "IXGBE_DPMCS"}, + {IXGBE_PDPMCS, 1, 1, "IXGBE_PDPMCS"}, + {IXGBE_RUPPBMR, 1, 1, "IXGBE_RUPPBMR"}, + {IXGBE_RT2CR(0), 8, 4, "IXGBE_RT2CR"}, + {IXGBE_RT2SR(0), 8, 4, "IXGBE_RT2SR"}, + {IXGBE_TDTQ2TCCR(0), 8, 0x40, "IXGBE_TDTQ2TCCR"}, + {IXGBE_TDTQ2TCSR(0), 8, 0x40, "IXGBE_TDTQ2TCSR"}, + {IXGBE_TDPT2TCCR(0), 8, 4, "IXGBE_TDPT2TCCR"}, + {IXGBE_TDPT2TCSR(0), 8, 4, "IXGBE_TDPT2TCSR"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_mac [] = { + {IXGBE_PCS1GCFIG, 1, 1, "IXGBE_PCS1GCFIG"}, + {IXGBE_PCS1GLCTL, 1, 1, "IXGBE_PCS1GLCTL"}, + {IXGBE_PCS1GLSTA, 1, 1, "IXGBE_PCS1GLSTA"}, + {IXGBE_PCS1GDBG0, 1, 1, "IXGBE_PCS1GDBG0"}, + {IXGBE_PCS1GDBG1, 1, 1, "IXGBE_PCS1GDBG1"}, + {IXGBE_PCS1GANA, 1, 1, "IXGBE_PCS1GANA"}, + {IXGBE_PCS1GANLP, 1, 1, "IXGBE_PCS1GANLP"}, + {IXGBE_PCS1GANNP, 1, 1, "IXGBE_PCS1GANNP"}, + {IXGBE_PCS1GANLPNP, 1, 1, "IXGBE_PCS1GANLPNP"}, + {IXGBE_HLREG0, 1, 1, "IXGBE_HLREG0"}, + {IXGBE_HLREG1, 1, 1, "IXGBE_HLREG1"}, + {IXGBE_PAP, 1, 1, "IXGBE_PAP"}, + {IXGBE_MACA, 1, 1, "IXGBE_MACA"}, + {IXGBE_APAE, 1, 1, "IXGBE_APAE"}, + {IXGBE_ARD, 1, 1, "IXGBE_ARD"}, + {IXGBE_AIS, 1, 1, "IXGBE_AIS"}, + {IXGBE_MSCA, 1, 1, "IXGBE_MSCA"}, + {IXGBE_MSRWD, 1, 1, "IXGBE_MSRWD"}, + {IXGBE_MLADD, 1, 1, "IXGBE_MLADD"}, + {IXGBE_MHADD, 1, 1, "IXGBE_MHADD"}, + {IXGBE_TREG, 1, 1, "IXGBE_TREG"}, + {IXGBE_PCSS1, 1, 1, "IXGBE_PCSS1"}, + {IXGBE_PCSS2, 1, 1, "IXGBE_PCSS2"}, + {IXGBE_XPCSS, 1, 1, "IXGBE_XPCSS"}, + {IXGBE_SERDESC, 1, 1, "IXGBE_SERDESC"}, + {IXGBE_MACS, 1, 1, "IXGBE_MACS"}, + {IXGBE_AUTOC, 1, 1, "IXGBE_AUTOC"}, + {IXGBE_LINKS, 1, 1, "IXGBE_LINKS"}, + {IXGBE_AUTOC2, 1, 1, "IXGBE_AUTOC2"}, + {IXGBE_AUTOC3, 1, 1, "IXGBE_AUTOC3"}, + {IXGBE_ANLP1, 1, 1, "IXGBE_ANLP1"}, + {IXGBE_ANLP2, 1, 1, "IXGBE_ANLP2"}, + {IXGBE_ATLASCTL, 1, 1, "IXGBE_ATLASCTL"}, + {0, 0, 0, ""} +}; + +static reg_info ixgbe_regs_diagnostic [] = { + {IXGBE_RDSTATCTL, 1, 1, "IXGBE_RDSTATCTL"}, + {IXGBE_RDSTAT(0), 8, 4, "IXGBE_RDSTAT"}, + {IXGBE_RDHMPN, 1, 1, "IXGBE_RDHMPN"}, + {IXGBE_RIC_DW(0), 4, 4, "IXGBE_RIC_DW"}, + {IXGBE_RDPROBE, 1, 1, "IXGBE_RDPROBE"}, + {IXGBE_TDHMPN, 1, 1, "IXGBE_TDHMPN"}, + {IXGBE_TIC_DW(0), 4, 4, "IXGBE_TIC_DW"}, + {IXGBE_TDPROBE, 1, 1, "IXGBE_TDPROBE"}, + {IXGBE_TXBUFCTRL, 1, 1, "IXGBE_TXBUFCTRL"}, + {IXGBE_TXBUFDATA0, 1, 1, "IXGBE_TXBUFDATA0"}, + {IXGBE_TXBUFDATA1, 1, 1, "IXGBE_TXBUFDATA1"}, + {IXGBE_TXBUFDATA2, 1, 1, "IXGBE_TXBUFDATA2"}, + {IXGBE_TXBUFDATA3, 1, 1, "IXGBE_TXBUFDATA3"}, + {IXGBE_RXBUFCTRL, 1, 1, "IXGBE_RXBUFCTRL"}, + {IXGBE_RXBUFDATA0, 1, 1, "IXGBE_RXBUFDATA0"}, + {IXGBE_RXBUFDATA1, 1, 1, "IXGBE_RXBUFDATA1"}, + {IXGBE_RXBUFDATA2, 1, 1, "IXGBE_RXBUFDATA2"}, + {IXGBE_RXBUFDATA3, 1, 1, "IXGBE_RXBUFDATA3"}, + {IXGBE_PCIE_DIAG(0), 8, 4, ""}, + {IXGBE_RFVAL, 1, 1, "IXGBE_RFVAL"}, + {IXGBE_MDFTC1, 1, 1, "IXGBE_MDFTC1"}, + {IXGBE_MDFTC2, 1, 1, "IXGBE_MDFTC2"}, + {IXGBE_MDFTFIFO1, 1, 1, "IXGBE_MDFTFIFO1"}, + {IXGBE_MDFTFIFO2, 1, 1, "IXGBE_MDFTFIFO2"}, + {IXGBE_MDFTS, 1, 1, "IXGBE_MDFTS"}, + {IXGBE_PCIEECCCTL, 1, 1, "IXGBE_PCIEECCCTL"}, + {IXGBE_PBTXECC, 1, 1, "IXGBE_PBTXECC"}, + {IXGBE_PBRXECC, 1, 1, "IXGBE_PBRXECC"}, + {IXGBE_MFLCN, 1, 1, "IXGBE_MFLCN"}, + {0, 0, 0, ""}, +}; + +/* PF registers */ +static reg_info* ixgbe_regs_others[] = { ixgbe_regs_general, ixgbe_regs_nvm, ixgbe_regs_interrupt, + ixgbe_regs_fctl_others, ixgbe_regs_rxdma, ixgbe_regs_rx, + ixgbe_regs_tx, ixgbe_regs_wakeup, ixgbe_regs_dcb, + ixgbe_regs_mac, ixgbe_regs_diagnostic, NULL}; + +static reg_info* ixgbe_regs_mac_82598EB[] = { ixgbe_regs_general, ixgbe_regs_nvm, ixgbe_regs_interrupt, + ixgbe_regs_fctl_mac_82598EB, ixgbe_regs_rxdma, ixgbe_regs_rx, + ixgbe_regs_tx, ixgbe_regs_wakeup, ixgbe_regs_dcb, + ixgbe_regs_mac, ixgbe_regs_diagnostic, NULL}; + +/* VF registers */ +static reg_info* ixgbevf_regs[] = { ixgbevf_regs_general, ixgbevf_regs_interrupt, + ixgbevf_regs_rxdma, ixgbevf_regs_tx, NULL}; + +static inline int +ixgbe_read_regs(struct ixgbe_hw *hw, reg_info *reg, uint32_t *reg_buf) +{ + unsigned int i; + + for(i = 0; i < reg->count; i++) { + reg_buf[i] = IXGBE_READ_REG(hw, reg->base_addr + i*reg->stride); + } + return reg->count; +}; + +static inline int +ixgbe_regs_group_count(reg_info *regs) +{ + int count = 0; + int i = 0; + + while (regs[i].count) { + count += regs[i].count; + i++; + } + return count; +}; + +static inline int +ixgbe_read_regs_group(struct rte_eth_dev *dev, uint32_t *reg_buf, reg_info *regs) +{ + int count = 0; + int i = 0; + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + while (regs[i].count) { + count += ixgbe_read_regs(hw, ®s[i], ®_buf[count]); + i++; + } + return count; +}; + +#endif // _IXGBE_REGS_H_ diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 4f9ab22..762d303 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -2448,6 +2448,22 @@ ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) return desc; } +uint32_t +ixgbe_dev_tx_queue_count(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct ixgbe_tx_queue *txq; + + if (tx_queue_id >= dev->data->nb_tx_queues) { + PMD_TX_LOG(ERR, "Invalid TX queue id=%d", tx_queue_id); + return 0; + } + + txq = dev->data->tx_queues[tx_queue_id]; + if (txq->tx_ring[txq->tx_next_dd].wb.status & IXGBE_ADVTXD_STAT_DD) + return (txq->nb_tx_free + txq->tx_rs_thresh); + return txq->nb_tx_free; +} + int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset) { diff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxtx.h index af36438..3b3163c 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.h +++ b/drivers/net/ixgbe/ixgbe_rxtx.h @@ -282,6 +282,7 @@ uint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); int ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev); int ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq); +uint32_t ixgbe_dev_tx_queue_count(struct rte_eth_dev *dev, uint16_t tx_queue_id); #ifdef RTE_IXGBE_INC_VECTOR -- 2.1.4