From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id BF463C4D4 for ; Wed, 29 Jul 2015 05:22:08 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 28 Jul 2015 20:22:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,568,1432623600"; d="scan'208";a="737593231" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga001.jf.intel.com with ESMTP; 28 Jul 2015 20:22:07 -0700 Received: from shecgisg003.sh.intel.com (shecgisg003.sh.intel.com [10.239.29.90]) by shvmail01.sh.intel.com with ESMTP id t6T3M4Cx025489; Wed, 29 Jul 2015 11:22:04 +0800 Received: from shecgisg003.sh.intel.com (localhost [127.0.0.1]) by shecgisg003.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t6T3M2xJ009047; Wed, 29 Jul 2015 11:22:04 +0800 Received: (from yliu84x@localhost) by shecgisg003.sh.intel.com (8.13.6/8.13.6/Submit) id t6T3M2AP009043; Wed, 29 Jul 2015 11:22:02 +0800 From: Yong Liu To: dev@dpdk.org Date: Wed, 29 Jul 2015 11:22:01 +0800 Message-Id: <1438140121-9011-1-git-send-email-yong.liu@intel.com> X-Mailer: git-send-email 1.7.4.1 Subject: [dpdk-dev] [PATCH] app test: fix mempool cache_size not match limited cache_size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Jul 2015 03:22:09 -0000 From: Marvin Liu In previous setting, mempool size and cache_size are both 32. This is not satisfied with cache_size checking rule by now. Cache size should less than CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE and mempool size / 1.5. Signed-off-by: Marvin Liu diff --git a/app/test/test_sched.c b/app/test/test_sched.c index 1ef6910..7a38db3 100644 --- a/app/test/test_sched.c +++ b/app/test/test_sched.c @@ -87,7 +87,7 @@ static struct rte_sched_port_params port_param = { #define NB_MBUF 32 #define MBUF_DATA_SZ (2048 + RTE_PKTMBUF_HEADROOM) -#define PKT_BURST_SZ 32 +#define PKT_BURST_SZ 0 #define MEMPOOL_CACHE_SZ PKT_BURST_SZ #define SOCKET 0 -- 1.9.3