From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 153588E6F for ; Thu, 24 Sep 2015 09:16:30 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 24 Sep 2015 00:16:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,579,1437462000"; d="scan'208";a="567494424" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by FMSMGA003.fm.intel.com with ESMTP; 24 Sep 2015 00:16:28 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t8O7GQiH020705; Thu, 24 Sep 2015 15:16:26 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t8O7GM4Q020815; Thu, 24 Sep 2015 15:16:24 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t8O7GMCR020811; Thu, 24 Sep 2015 15:16:22 +0800 From: Helin Zhang To: dev@dpdk.org Date: Thu, 24 Sep 2015 15:16:18 +0800 Message-Id: <1443078979-20774-2-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1443078979-20774-1-git-send-email-helin.zhang@intel.com> References: <1443078979-20774-1-git-send-email-helin.zhang@intel.com> Cc: yulong.pei@intel.com Subject: [dpdk-dev] [PATCH 1/2] i40e: add selecting GRE key length X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Sep 2015 07:16:31 -0000 By default, only first 3 bytes of GRE key will be used for hash or filter calculation. With these changes, it can select 3 or 4 bytes of GRE key for hash calculation. Signed-off-by: Helin Zhang Signed-off-by: Andrey Chilikin --- drivers/net/i40e/i40e_ethdev.c | 86 +++++++++++++++++++++++++++++++++++++++-- lib/librte_ether/rte_eth_ctrl.h | 20 ++++++++++ 2 files changed, 103 insertions(+), 3 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 77e6906..b88a2f0 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -5328,7 +5328,7 @@ i40e_pf_config_rss(struct i40e_pf *pf) static int i40e_tunnel_filter_param_check(struct i40e_pf *pf, - struct rte_eth_tunnel_filter_conf *filter) + struct rte_eth_tunnel_filter_conf *filter) { if (pf == NULL || filter == NULL) { PMD_DRV_LOG(ERR, "Invalid parameter"); @@ -5360,9 +5360,84 @@ i40e_tunnel_filter_param_check(struct i40e_pf *pf, return 0; } +#define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) static int -i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op, - void *arg) +i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len) +{ + uint32_t val, reg; + int ret = -EINVAL; + + val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)); + PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val); + + if (len == 3) { + reg = val | 0x80000000; + } else if (len == 4) { + reg = val & ~0x80000000; + } else { + PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len); + return ret; + } + + if (reg != val) { + ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2), + reg, NULL); + if (ret != 0) + return ret; + } else { + ret = 0; + } + PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n", + I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2))); + + return ret; +} + +static int +i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg) +{ + int ret = -EINVAL; + + if (!hw || !cfg) + return -EINVAL; + + switch (cfg->cfg_type) { + case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN: + ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len); + break; + default: + PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type); + break; + } + + return ret; +} + +static int +i40e_filter_ctrl_global_config(struct rte_eth_dev *dev, + enum rte_filter_op filter_op, + void *arg) +{ + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int ret = I40E_ERR_PARAM; + + switch (filter_op) { + case RTE_ETH_FILTER_SET: + ret = i40e_dev_global_config_set(hw, + (struct rte_eth_global_cfg *)arg); + break; + default: + PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); + break; + } + + return ret; +} + +static int +i40e_tunnel_filter_handle(struct rte_eth_dev *dev, + enum rte_filter_op filter_op, + void *arg) { struct rte_eth_tunnel_filter_conf *filter; struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); @@ -5377,6 +5452,7 @@ i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op, case RTE_ETH_FILTER_NOP: if (!(pf->flags & I40E_FLAG_VXLAN)) ret = I40E_NOT_SUPPORTED; + break; case RTE_ETH_FILTER_ADD: ret = i40e_dev_tunnel_filter_set(pf, filter, 1); break; @@ -6268,6 +6344,10 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev, return -EINVAL; switch (filter_type) { + case RTE_ETH_FILTER_NONE: + /* For global configuration */ + ret = i40e_filter_ctrl_global_config(dev, filter_op, arg); + break; case RTE_ETH_FILTER_HASH: ret = i40e_hash_filter_ctrl(dev, filter_op, arg); break; diff --git a/lib/librte_ether/rte_eth_ctrl.h b/lib/librte_ether/rte_eth_ctrl.h index a7f2ee7..78f5cd1 100644 --- a/lib/librte_ether/rte_eth_ctrl.h +++ b/lib/librte_ether/rte_eth_ctrl.h @@ -295,6 +295,26 @@ struct rte_eth_tunnel_filter_conf { uint16_t queue_id; /** < queue number. */ }; +/** + * Global eth device configuration type. + */ +enum rte_eth_global_cfg_type { + RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0, + RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN, + RTE_ETH_GLOBAL_CFG_TYPE_MAX, +}; + +/** + * Global eth device configuration. + */ +struct rte_eth_global_cfg { + enum rte_eth_global_cfg_type cfg_type; /**< Global config type. */ + union { + uint8_t gre_key_len; /**< Valid GRE key length in byte. */ + uint64_t reserved; /**< Reserve space for future use. */ + } cfg; +}; + #define RTE_ETH_FDIR_MAX_FLEXLEN 16 /** < Max length of flexbytes. */ #define RTE_ETH_INSET_SIZE_MAX 128 /** < Max length of input set. */ -- 1.9.3