From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id E1A66E72 for ; Wed, 30 Sep 2015 21:36:09 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 30 Sep 2015 12:36:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,613,1437462000"; d="scan'208";a="800785482" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga001.fm.intel.com with ESMTP; 30 Sep 2015 12:36:08 -0700 Received: from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com [10.237.217.46]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id t8UJ4XP5002996; Wed, 30 Sep 2015 20:04:33 +0100 Received: from sivswdev02.ir.intel.com (localhost [127.0.0.1]) by sivswdev02.ir.intel.com with ESMTP id t8UJ4XEZ021077; Wed, 30 Sep 2015 20:04:33 +0100 Received: (from kananye1@localhost) by sivswdev02.ir.intel.com with id t8UJ4WB0021073; Wed, 30 Sep 2015 20:04:32 +0100 From: Konstantin Ananyev To: dev@dpdk.org Date: Wed, 30 Sep 2015 20:04:30 +0100 Message-Id: <1443639870-20879-1-git-send-email-konstantin.ananyev@intel.com> X-Mailer: git-send-email 1.7.4.1 Subject: [dpdk-dev] [PATCH] i40e: fix wrong alignment for the number of HW descriptors X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Sep 2015 19:36:10 -0000 According to XL710 datasheet: RX QLEN restrictions: When the PXE_MODE flag in the GLLAN_RCTL_0 register is cleared, the QLEN must be whole number of 32 descriptors. TX QLEN restrictions: When the PXE_MODE flag in the GLLAN_RCTL_0 register is cleared, the QLEN must be whole number of 32 descriptors. So make sure that for both RX and TX queues number of HW descriptors is a multiple of 32. Signed-off-by: Konstantin Ananyev --- drivers/net/i40e/i40e_rxtx.c | 26 +++++++++++++------------- drivers/net/i40e/i40e_rxtx.h | 6 ++++++ 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index fd656d5..260e580 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -57,9 +57,6 @@ #include "i40e_ethdev.h" #include "i40e_rxtx.h" -#define I40E_MIN_RING_DESC 64 -#define I40E_MAX_RING_DESC 4096 -#define I40E_ALIGN 128 #define DEFAULT_TX_RS_THRESH 32 #define DEFAULT_TX_FREE_THRESH 32 #define I40E_MAX_PKT_TYPE 256 @@ -68,6 +65,9 @@ #define I40E_DMA_MEM_ALIGN 4096 +/* Base address of the HW descriptor ring should be 128B aligned. */ +#define I40E_RING_BASE_ALIGN 128 + #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \ ETH_TXQ_FLAGS_NOOFFLOADS) @@ -2126,9 +2126,9 @@ i40e_dev_rx_queue_setup(struct rte_eth_dev *dev, "index exceeds the maximum"); return I40E_ERR_PARAM; } - if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 || - (nb_desc > I40E_MAX_RING_DESC) || - (nb_desc < I40E_MIN_RING_DESC)) { + if (nb_desc % I40E_ALIGN_RING_DESC != 0 || + (nb_desc > I40E_MAX_RING_DESC) || + (nb_desc < I40E_MIN_RING_DESC)) { PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is " "invalid", nb_desc); return I40E_ERR_PARAM; @@ -2338,9 +2338,9 @@ i40e_dev_tx_queue_setup(struct rte_eth_dev *dev, return I40E_ERR_PARAM; } - if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 || - (nb_desc > I40E_MAX_RING_DESC) || - (nb_desc < I40E_MIN_RING_DESC)) { + if (nb_desc % I40E_ALIGN_RING_DESC != 0 || + (nb_desc > I40E_MAX_RING_DESC) || + (nb_desc < I40E_MIN_RING_DESC)) { PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is " "invalid", nb_desc); return I40E_ERR_PARAM; @@ -2537,10 +2537,10 @@ i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev, #ifdef RTE_LIBRTE_XEN_DOM0 return rte_memzone_reserve_bounded(z_name, ring_size, - socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M); + socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M); #else return rte_memzone_reserve_aligned(z_name, ring_size, - socket_id, 0, I40E_ALIGN); + socket_id, 0, I40E_RING_BASE_ALIGN); #endif } @@ -2554,10 +2554,10 @@ i40e_memzone_reserve(const char *name, uint32_t len, int socket_id) return mz; #ifdef RTE_LIBRTE_XEN_DOM0 mz = rte_memzone_reserve_bounded(name, len, - socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M); + socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M); #else mz = rte_memzone_reserve_aligned(name, len, - socket_id, 0, I40E_ALIGN); + socket_id, 0, I40E_RING_BASE_ALIGN); #endif return mz; } diff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h index 4385142..3d9884d 100644 --- a/drivers/net/i40e/i40e_rxtx.h +++ b/drivers/net/i40e/i40e_rxtx.h @@ -51,6 +51,12 @@ #define I40E_RXBUF_SZ_1024 1024 #define I40E_RXBUF_SZ_2048 2048 +/* In none-PXE mode QLEN must be whole number of 32 descriptors. */ +#define I40E_ALIGN_RING_DESC 32 + +#define I40E_MIN_RING_DESC 64 +#define I40E_MAX_RING_DESC 4096 + enum i40e_header_split_mode { i40e_header_split_none = 0, i40e_header_split_enabled = 1, -- 1.8.5.3