From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 19D568E68 for ; Fri, 30 Oct 2015 10:46:03 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 30 Oct 2015 02:46:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,217,1444719600"; d="scan'208";a="838722808" Received: from unknown ([10.217.248.15]) by orsmga002.jf.intel.com with SMTP; 30 Oct 2015 02:46:01 -0700 Received: by (sSMTP sendmail emulation); Fri, 30 Oct 2015 10:45:18 +0100 From: Daniel Mrzyglod To: dev@dpdk.org Date: Fri, 30 Oct 2015 10:43:20 +0100 Message-Id: <1446198204-9852-3-git-send-email-danielx.t.mrzyglod@intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1446198204-9852-1-git-send-email-danielx.t.mrzyglod@intel.com> References: <1443799208-9408-1-git-send-email-danielx.t.mrzyglod@intel.com> <1446198204-9852-1-git-send-email-danielx.t.mrzyglod@intel.com> Subject: [dpdk-dev] [PATCH v2 2/6] ixgbe: add additional ieee1588 support functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Oct 2015 09:46:05 -0000 Add additional functions to support the existing IEEE1588 functionality and to enable getting, setting and adjusting the device time. Signed-off-by: Daniel Mrzyglod Signed-off-by: Pablo de Lara --- drivers/net/ixgbe/ixgbe_ethdev.c | 313 +++++++++++++++++++++++++++++++++++++-- drivers/net/ixgbe/ixgbe_ethdev.h | 22 +++ 2 files changed, 324 insertions(+), 11 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 4373661..2c39501 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -126,10 +126,17 @@ #define IXGBE_HKEY_MAX_INDEX 10 /* Additional timesync values. */ -#define IXGBE_TIMINCA_16NS_SHIFT 24 -#define IXGBE_TIMINCA_INCVALUE 16000000 -#define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \ - | IXGBE_TIMINCA_INCVALUE) +#define NSEC_PER_SEC 1000000000L +#define IXGBE_INCVAL_10GB 0x66666666 +#define IXGBE_INCVAL_1GB 0x40000000 +#define IXGBE_INCVAL_100 0x50000000 +#define IXGBE_INCVAL_SHIFT_10GB 28 +#define IXGBE_INCVAL_SHIFT_1GB 24 +#define IXGBE_INCVAL_SHIFT_100 21 +#define IXGBE_INCVAL_SHIFT_82599 7 +#define IXGBE_INCPER_SHIFT_82599 24 + +#define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffff static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev); static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); @@ -325,6 +332,11 @@ static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, uint32_t flags); static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, struct timespec *timestamp); +static int ixgbe_timesync_time_adjust(struct rte_eth_dev *dev, int64_t delta); +static int ixgbe_timesync_time_get(struct rte_eth_dev *dev, + struct timespec *timestamp); +static int ixgbe_timesync_time_set(struct rte_eth_dev *dev, + struct timespec *timestamp); /* * Define VF Stats MACRO for Non "cleared on read" register @@ -465,6 +477,9 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = { .get_eeprom_length = ixgbe_get_eeprom_length, .get_eeprom = ixgbe_get_eeprom, .set_eeprom = ixgbe_set_eeprom, + .timesync_time_adjust = ixgbe_timesync_time_adjust, + .timesync_time_get = ixgbe_timesync_time_get, + .timesync_time_set = ixgbe_timesync_time_set, }; /* @@ -5267,20 +5282,273 @@ ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, ixgbe_dev_addr_list_itr, TRUE); } +static inline uint64_t +timespec_to_ns(const struct timespec *ts) +{ + return ((uint64_t) ts->tv_sec * NSEC_PER_SEC) + ts->tv_nsec; +} + +static struct timespec +ns_to_timespec(uint64_t nsec) +{ + struct timespec ts = {0, 0}; + + if (nsec == 0) + return ts; + + ts.tv_sec = nsec / NSEC_PER_SEC; + ts.tv_nsec = nsec % NSEC_PER_SEC; + + return ts; +} + +/* + * Converts cycle counter cycles to nanoseconds. + */ +static inline uint64_t +cyclecounter_cycles_to_ns(const struct cyclecounter *cc, + uint64_t cycles, uint64_t mask, uint64_t *frac) +{ + uint64_t ns; + + /* Add fractional nanoseconds */ + ns = cycles + *frac; + *frac = ns & mask; + + /* Shift to get only nanoseconds. */ + return ns >> cc->shift; +} + +/* + * Like cyclecounter_cycles_to_ns(), but this is used when + * computing a time previous to the stored in the cycle counter. + */ +static uint64_t +cyclecounter_cycles_to_ns_backwards(const struct cyclecounter *cc, + uint64_t cycles, uint64_t frac) +{ + return ((cycles - frac) >> cc->shift); +} + +/* + * Register units might not be nanoseconds. This function converts + * these units into nanoseconds and adds to the previous time stored. + */ +static uint64_t +timecounter_cycles_to_ns_time(struct timecounter *tc, uint64_t cycle_tstamp) +{ + uint64_t delta; + uint64_t nsec = tc->nsec, frac = tc->frac; + + delta = (cycle_tstamp - tc->cycle_last) & tc->cc->mask; + /* + * Cycle counts that are correctly converted as they + * are between -1/2 max cycle count and +1/2 max cycle count. + */ + if (delta > (tc->cc->mask / 2)) { + delta = (tc->cycle_last - cycle_tstamp) & tc->cc->mask; + nsec -= cyclecounter_cycles_to_ns_backwards(tc->cc, delta, frac); + } else { + nsec += cyclecounter_cycles_to_ns(tc->cc, delta, tc->mask, &frac); + } + + return nsec; +} + +static uint64_t +ixgbe_read_timesync_cyclecounter(struct rte_eth_dev *dev) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint64_t systime_cycles = 0; + + switch (hw->mac.type) { + case ixgbe_mac_X550: + /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ + systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); + systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) + * NSEC_PER_SEC; + break; + default: + systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); + systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) + << 32; + } + + return systime_cycles; +} + +/* + * Get nanoseconds since the last call of this function. + */ +static uint64_t +timecounter_read_ns_delta(struct rte_eth_dev *dev) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint64_t cycle_now, cycle_delta; + uint64_t ns_offset; + struct ixgbe_adapter *adapter = + (struct ixgbe_adapter *)dev->data->dev_private; + + /* Read cycle counter. */ + cycle_now = adapter->tc.cc->read(dev); + + /* Calculate the delta since the last timecounter_read_delta(). */ + cycle_delta = (cycle_now - adapter->tc.cycle_last) & adapter->tc.cc->mask; + + /* Convert to nanoseconds. */ + if (hw->mac.type == ixgbe_mac_X550) + /* Registers store directly nanoseconds, no need to convert. */ + ns_offset = cycle_delta; + else + ns_offset = cyclecounter_cycles_to_ns(adapter->tc.cc, cycle_delta, + adapter->tc.mask, &adapter->tc.frac); + + /* Store current cycle counter for next timecounter_read_ns_delta() call. */ + adapter->tc.cycle_last = cycle_now; + + return ns_offset; +} + +static uint64_t +timecounter_read(struct rte_eth_dev *dev) +{ + uint64_t nsec; + struct ixgbe_adapter *adapter = + (struct ixgbe_adapter *)dev->data->dev_private; + + /* Increment time by nanoseconds since last call. */ + nsec = timecounter_read_ns_delta(dev); + nsec += adapter->tc.nsec; + adapter->tc.nsec = nsec; + + return nsec; +} + + +static void +timecounter_init(struct rte_eth_dev *dev, + uint64_t start_time) +{ + struct ixgbe_adapter *adapter = + (struct ixgbe_adapter *)dev->data->dev_private; + adapter->tc.cc = &adapter->cc; + adapter->tc.cycle_last = adapter->tc.cc->read(dev); + adapter->tc.nsec = start_time; + adapter->tc.mask = (1ULL << adapter->tc.cc->shift) - 1; + adapter->tc.frac = 0; +} + +static void +ixgbe_start_cyclecounter(struct rte_eth_dev *dev) +{ + struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ixgbe_adapter *adapter = + (struct ixgbe_adapter *)dev->data->dev_private; + struct rte_eth_link link; + uint32_t incval = 0; + uint32_t shift = 0; + + /* Get current link speed. */ + memset(&link, 0, sizeof(link)); + ixgbe_dev_link_update(dev, 1); + rte_ixgbe_dev_atomic_read_link_status(dev, &link); + + switch (link.link_speed) { + case ETH_LINK_SPEED_100: + incval = IXGBE_INCVAL_100; + shift = IXGBE_INCVAL_SHIFT_100; + break; + case ETH_LINK_SPEED_1000: + incval = IXGBE_INCVAL_1GB; + shift = IXGBE_INCVAL_SHIFT_1GB; + break; + case ETH_LINK_SPEED_10000: + default: + incval = IXGBE_INCVAL_10GB; + shift = IXGBE_INCVAL_SHIFT_10GB; + break; + } + + switch (hw->mac.type) { + case ixgbe_mac_X550: + /* Independent of link speed. */ + incval = 1; + /* Cycles read will be interpreted as ns. */ + shift = 0; + /* Fall-through */ + case ixgbe_mac_X540: + IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); + break; + case ixgbe_mac_82599EB: + incval >>= IXGBE_INCVAL_SHIFT_82599; + shift -= IXGBE_INCVAL_SHIFT_82599; + IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, + (1 << IXGBE_INCPER_SHIFT_82599) | incval); + break; + default: + /* Not supported. */ + return; + } + + memset(&adapter->cc, 0, sizeof(struct cyclecounter)); + adapter->cc.read = ixgbe_read_timesync_cyclecounter; + adapter->cc.mask = IXGBE_CYCLECOUNTER_MASK; + adapter->cc.shift = shift; +} + +static int +ixgbe_timesync_time_adjust(struct rte_eth_dev *dev, int64_t delta) +{ + struct ixgbe_adapter *adapter = + (struct ixgbe_adapter *)dev->data->dev_private; + + adapter->tc.nsec += delta; + + return 0; +} + +static int +ixgbe_timesync_time_set(struct rte_eth_dev *dev, struct timespec *ts) +{ + uint64_t ns; + + ns = timespec_to_ns(ts); + /* Reset the timecounter. */ + timecounter_init(dev, ns); + + return 0; +} + +static int +ixgbe_timesync_time_get(struct rte_eth_dev *dev, struct timespec *ts) +{ + uint64_t ns; + + ns = timecounter_read(dev); + *ts = ns_to_timespec(ns); + + return 0; +} + static int ixgbe_timesync_enable(struct rte_eth_dev *dev) { struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint32_t tsync_ctl; uint32_t tsauxc; + uint64_t ns; + struct timespec zerotime = {0, 0}; /* Enable system time for platforms where it isn't on by default. */ tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; - IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); - /* Start incrementing the register used to timestamp PTP packets. */ - IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT); + /* Set 0.0 epoch time to initialize timecounter. */ + ns = timespec_to_ns(&zerotime); + ixgbe_start_cyclecounter(dev); + timecounter_init(dev, ns); + + IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), @@ -5298,6 +5566,9 @@ ixgbe_timesync_enable(struct rte_eth_dev *dev) tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); + /* After writing to registers should be flush. */ + IXGBE_WRITE_FLUSH(hw); + return 0; } @@ -5332,9 +5603,13 @@ ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, uint32_t flags __rte_unused) { struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ixgbe_adapter *adapter = + (struct ixgbe_adapter *)dev->data->dev_private; + uint32_t tsync_rxctl; uint32_t rx_stmpl; uint32_t rx_stmph; + uint64_t regival = 0; tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) @@ -5342,9 +5617,15 @@ ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL); rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH); + timecounter_read(dev); - timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl); - timestamp->tv_nsec = 0; + if (hw->mac.type == ixgbe_mac_X550) + regival = (uint64_t)((uint64_t) rx_stmph * NSEC_PER_SEC + + rx_stmpl); + else + regival = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl); + regival = timecounter_cycles_to_ns_time(&adapter->tc, regival); + *timestamp = ns_to_timespec(regival); return 0; } @@ -5354,9 +5635,13 @@ ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, struct timespec *timestamp) { struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ixgbe_adapter *adapter = + (struct ixgbe_adapter *)dev->data->dev_private; + uint32_t tsync_txctl; uint32_t tx_stmpl; uint32_t tx_stmph; + uint64_t regival = 0; tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) @@ -5364,9 +5649,15 @@ ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL); tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH); + timecounter_read(dev); - timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl); - timestamp->tv_nsec = 0; + if (hw->mac.type == ixgbe_mac_X550) + regival = (uint64_t)((uint64_t) tx_stmph * NSEC_PER_SEC + + tx_stmpl); + else + regival = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl); + regival = timecounter_cycles_to_ns_time(&adapter->tc, regival); + *timestamp = ns_to_timespec(regival); return 0; } diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h index f75c6dd..2ace8c0 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.h +++ b/drivers/net/ixgbe/ixgbe_ethdev.h @@ -255,6 +255,26 @@ struct ixgbe_filter_info { }; /* + * Structure for cyclecounter IEEE1588 functionality. + */ +struct cyclecounter { + uint64_t (*read)(struct rte_eth_dev *dev); + uint64_t mask; + uint32_t shift; +}; + +/* + * Structure to hold and calculate Unix epoch time. + */ +struct timecounter { + struct cyclecounter *cc; + uint64_t cycle_last; + uint64_t nsec; + uint64_t mask; + uint64_t frac; +}; + +/* * Structure to store private data for each driver instance (for each port). */ struct ixgbe_adapter { @@ -276,6 +296,8 @@ struct ixgbe_adapter { bool rx_bulk_alloc_allowed; bool rx_vec_allowed; + struct cyclecounter cc; + struct timecounter tc; }; #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\ -- 2.1.0