From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 06BB091CC for ; Thu, 12 Nov 2015 13:55:59 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 12 Nov 2015 04:55:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,281,1444719600"; d="scan'208";a="835527505" Received: from sie-lab-214-214.ir.intel.com (HELO sie-lab-214-174.ir.intel.com) ([10.237.214.214]) by fmsmga001.fm.intel.com with ESMTP; 12 Nov 2015 04:55:57 -0800 From: Pablo de Lara To: dev@dpdk.org Date: Thu, 12 Nov 2015 12:55:35 +0000 Message-Id: <1447332938-201120-6-git-send-email-pablo.de.lara.guarch@intel.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1447332938-201120-1-git-send-email-pablo.de.lara.guarch@intel.com> References: <1446732366-10044-1-git-send-email-danielx.t.mrzyglod@intel.com> <1447332938-201120-1-git-send-email-pablo.de.lara.guarch@intel.com> Subject: [dpdk-dev] [PATCH v6 5/8] i40e: add additional ieee1588 support functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Nov 2015 12:56:00 -0000 Add additional functions to support the existing IEEE1588 functionality and to enable getting, setting and adjusting the device time. Signed-off-by: Daniel Mrzyglod Signed-off-by: Pablo de Lara Reviewed-by: John McNamara --- drivers/net/i40e/i40e_ethdev.c | 147 +++++++++++++++++++++++++++++++++++------ drivers/net/i40e/i40e_ethdev.h | 6 +- 2 files changed, 132 insertions(+), 21 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index ddf3d38..d6b3311 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -125,11 +125,13 @@ (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \ (1UL << RTE_ETH_FLOW_L2_PAYLOAD)) -#define I40E_PTP_40GB_INCVAL 0x0199999999ULL -#define I40E_PTP_10GB_INCVAL 0x0333333333ULL -#define I40E_PTP_1GB_INCVAL 0x2000000000ULL -#define I40E_PRTTSYN_TSYNENA 0x80000000 -#define I40E_PRTTSYN_TSYNTYPE 0x0e000000 +/* Additional timesync values. */ +#define I40E_PTP_40GB_INCVAL 0x0199999999ULL +#define I40E_PTP_10GB_INCVAL 0x0333333333ULL +#define I40E_PTP_1GB_INCVAL 0x2000000000ULL +#define I40E_PRTTSYN_TSYNENA 0x80000000 +#define I40E_PRTTSYN_TSYNTYPE 0x0e000000 +#define I40E_CYCLECOUNTER_MASK 0xffffffffffffffff #define I40E_MAX_PERCENT 100 #define I40E_DEFAULT_DCB_APP_NUM 1 @@ -400,11 +402,20 @@ static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, struct timespec *timestamp); static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw); + +static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); + +static int i40e_timesync_read_time(struct rte_eth_dev *dev, + struct timespec *timestamp); +static int i40e_timesync_write_time(struct rte_eth_dev *dev, + const struct timespec *timestamp); + static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id); static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id); + static const struct rte_pci_id pci_id_i40e_map[] = { #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)}, #include "rte_pci_dev_ids.h" @@ -469,6 +480,9 @@ static const struct eth_dev_ops i40e_eth_dev_ops = { .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp, .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp, .get_dcb_info = i40e_dev_get_dcb_info, + .timesync_adjust_time = i40e_timesync_adjust_time, + .timesync_read_time = i40e_timesync_read_time, + .timesync_write_time = i40e_timesync_write_time, }; /* store statistics names and its offset in stats structure */ @@ -7738,17 +7752,36 @@ i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id) return 0; } -static int -i40e_timesync_enable(struct rte_eth_dev *dev) +static uint64_t +i40e_read_cyclecounter(void *arg) { + struct rte_eth_dev *dev = (struct rte_eth_dev *) arg; struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); - struct rte_eth_link *link = &dev->data->dev_link; - uint32_t tsync_ctl_l; - uint32_t tsync_ctl_h; + uint64_t systim_cycles = 0; + + systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L); + systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H) + << 32; + + return systim_cycles; +} + +static void +i40e_start_cyclecounter(struct rte_eth_dev *dev) +{ + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct i40e_adapter *adapter = + (struct i40e_adapter *)dev->data->dev_private; + struct rte_eth_link link; uint32_t tsync_inc_l; uint32_t tsync_inc_h; - switch (link->link_speed) { + /* Get current link speed. */ + memset(&link, 0, sizeof(link)); + i40e_dev_link_update(dev, 1); + rte_i40e_dev_atomic_read_link_status(dev, &link); + + switch (link.link_speed) { case ETH_LINK_SPEED_40G: tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF; tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32; @@ -7766,6 +7799,72 @@ i40e_timesync_enable(struct rte_eth_dev *dev) tsync_inc_h = 0x0; } + /* Set the timesync increment value. */ + I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l); + I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h); + + memset(&adapter->tc, 0, sizeof(struct rte_timecounter)); + adapter->tc.read = i40e_read_cyclecounter; + adapter->tc.cc_mask = I40E_CYCLECOUNTER_MASK; + adapter->tc.cc_shift = 0; + adapter->tc.arg = dev; +} + +static int +i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) +{ + struct i40e_adapter *adapter = + (struct i40e_adapter *)dev->data->dev_private; + + adapter->tc.nsec += delta; + + return 0; +} + +static int +i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) +{ + uint64_t ns; + struct i40e_adapter *adapter = + (struct i40e_adapter *)dev->data->dev_private; + + ns = rte_timespec_to_ns(ts); + + /* Reset the timecounter. */ + rte_timecounter_init(&adapter->tc, ns); + + return 0; +} + +static int +i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) +{ + uint64_t ns; + struct i40e_adapter *adapter = + (struct i40e_adapter *)dev->data->dev_private; + + ns = rte_timecounter_read(&adapter->tc); + *ts = rte_ns_to_timespec(ns); + + return 0; +} + +static int +i40e_timesync_enable(struct rte_eth_dev *dev) +{ + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct i40e_adapter *adapter = + (struct i40e_adapter *)dev->data->dev_private; + uint32_t tsync_ctl_l; + uint32_t tsync_ctl_h; + uint64_t ns; + struct timespec zerotime = {0, 0}; + + /* Set 0.0 epoch time to initialize timecounter. */ + ns = rte_timespec_to_ns(&zerotime); + i40e_start_cyclecounter(dev); + rte_timecounter_init(&adapter->tc, ns); + /* Clear timesync registers. */ I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H); @@ -7775,10 +7874,6 @@ i40e_timesync_enable(struct rte_eth_dev *dev) I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3)); I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H); - /* Set the timesync increment value. */ - I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l); - I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h); - /* Enable timestamping of PTP packets. */ tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); tsync_ctl_l |= I40E_PRTTSYN_TSYNENA; @@ -7810,7 +7905,7 @@ i40e_timesync_disable(struct rte_eth_dev *dev) I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); - /* Set the timesync increment value. */ + /* Reset the timesync increment value. */ I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); @@ -7822,10 +7917,14 @@ i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, struct timespec *timestamp, uint32_t flags) { struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct i40e_adapter *adapter = + (struct i40e_adapter *)dev->data->dev_private; + uint32_t sync_status; uint32_t rx_stmpl; uint32_t rx_stmph; uint32_t index = flags & 0x03; + uint64_t regival = 0; sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1); if ((sync_status & (1 << index)) == 0) @@ -7833,9 +7932,11 @@ i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index)); rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index)); + rte_timecounter_read(&adapter->tc); - timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl); - timestamp->tv_nsec = 0; + regival = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl); + regival = rte_timecounter_cycles_to_ns_time(&adapter->tc, regival); + *timestamp = rte_ns_to_timespec(regival); return 0; } @@ -7845,9 +7946,13 @@ i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, struct timespec *timestamp) { struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct i40e_adapter *adapter = + (struct i40e_adapter *)dev->data->dev_private; + uint32_t sync_status; uint32_t tx_stmpl; uint32_t tx_stmph; + uint64_t regival = 0; sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0) @@ -7855,9 +7960,11 @@ i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L); tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H); + rte_timecounter_read(&adapter->tc); - timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl); - timestamp->tv_nsec = 0; + regival = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl); + regival = rte_timecounter_cycles_to_ns_time(&adapter->tc, regival); + *timestamp = rte_ns_to_timespec(regival); return 0; } diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index d281935..b23d1a9 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -35,6 +35,7 @@ #define _I40E_ETHDEV_H_ #include +#include #define I40E_VLAN_TAG_SIZE 4 @@ -516,11 +517,14 @@ struct i40e_adapter { struct i40e_vf vf; }; - /* for vector PMD */ + /* For vector PMD */ bool rx_bulk_alloc_allowed; bool rx_vec_allowed; bool tx_simple_allowed; bool tx_vec_allowed; + + /* For PTP */ + struct rte_timecounter tc; }; int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); -- 1.8.1.4