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BLUPR0701MB1715; 5:g4vwCj+7rz2pbC48oJtLb0mu/1no3bSj+jKnb6KCNohAdHi1TS1XuXWsfCwr0/P1yrcl/YBsJNAaCW5aXUikw6sw3lVnpTgcmkQsOqoIzKCuElU2LGby1QKu+b8hod+/DYwQAe0s2dR7wYA6cvq5lQ==; 24:O0dHxLLTzXnKHuLlebXr8vxVbucn/JJezzn4Bpry3nMpvtYPvfWymI5KpXLfHRDoVOtsnbio+vMbqcjMTCyP1tZqHGWgzWJujGKO5CxzWDo= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2015 16:37:06.0461 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1715 Subject: [dpdk-dev] [PATCH v2 1/4] eal: Introduce new cache macro definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 Dec 2015 16:37:11 -0000 - RTE_CACHE_MIN_LINE_SIZE(Supported minimum cache line size) - __rte_cache_min_aligned(Force minimum cache line alignment) - RTE_CACHE_LINE_SIZE_LOG2(Express cache line size in terms of log2) Signed-off-by: Jerin Jacob Suggested-by: Konstantin Ananyev --- lib/librte_eal/common/include/rte_memory.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h index 9c9e40f..b67a76f 100644 --- a/lib/librte_eal/common/include/rte_memory.h +++ b/lib/librte_eal/common/include/rte_memory.h @@ -77,11 +77,27 @@ enum rte_page_sizes { (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) /**< Return the first cache-aligned value greater or equal to size. */ +/**< Cache line size in terms of log2 */ +#if RTE_CACHE_LINE_SIZE == 64 +#define RTE_CACHE_LINE_SIZE_LOG2 6 +#elif RTE_CACHE_LINE_SIZE == 128 +#define RTE_CACHE_LINE_SIZE_LOG2 7 +#else +#error "Unsupported cache line size" +#endif + +#define RTE_CACHE_MIN_LINE_SIZE 64 /**< Minimum Cache line size. */ + /** * Force alignment to cache line. */ #define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) +/** + * Force minimum cache line alignment. + */ +#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_MIN_LINE_SIZE) + typedef uint64_t phys_addr_t; /**< Physical address definition. */ #define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) -- 2.1.0