From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id E36FB58E4 for ; Thu, 21 Jan 2016 09:19:00 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP; 21 Jan 2016 00:18:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,324,1449561600"; d="scan'208";a="865266237" Received: from sie-lab-213-067.ir.intel.com (HELO silpixa00385445.ir.intel.com) ([10.237.213.67]) by orsmga001.jf.intel.com with ESMTP; 21 Jan 2016 00:18:34 -0800 From: Wojciech Andralojc To: dev@dpdk.org Date: Thu, 21 Jan 2016 08:18:07 +0000 Message-Id: <1453364287-37283-1-git-send-email-wojciechx.andralojc@intel.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <2601191342CEEE43887BDE71AB97725836AEC360@irsmsx105.ger.corp.intel.com> References: <2601191342CEEE43887BDE71AB97725836AEC360@irsmsx105.ger.corp.intel.com> Subject: [dpdk-dev] [PATCH v3] Patch introducing API to read/write Intel Architecture Model Specific Registers (MSR)... X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2016 08:19:02 -0000 Patch reworked. Signed-off-by: Wojciech Andralojc --- lib/librte_eal/common/include/arch/x86/rte_msr.h | 88 +++++++++++++++++ lib/librte_eal/linuxapp/eal/Makefile | 1 + lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c | 116 +++++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/x86/rte_msr.h create mode 100644 lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c diff --git a/lib/librte_eal/common/include/arch/x86/rte_msr.h b/lib/librte_eal/common/include/arch/x86/rte_msr.h new file mode 100644 index 0000000..fc49107 --- /dev/null +++ b/lib/librte_eal/common/include/arch/x86/rte_msr.h @@ -0,0 +1,88 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2016 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_MSR_X86_64_H_ +#define _RTE_MSR_X86_64_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file + * + * API to read/write Intel Architecture Model Specific Registers (MSR). + * + */ + +/** + * Function to read CPU's MSR + * + * @param [in] cpuid + * CPU logical core id + * + * @param [in] reg + * MSR reg to read + * + * @param [out] value + * Read value of MSR reg + * + * @return + * Operations status +*/ +extern int rte_msr_read(const unsigned cpuid, const uint32_t reg, + uint64_t *value); + +/** + * Function to write CPU's MSR + * + * @param [in] cpuid + * CPU logical core id + * + * @param [in] reg + * MSR reg to write + * + * @param [in] value + * Value to be written to MSR reg + * + * @return + * Operations status +*/ +extern int rte_msr_write(const unsigned cpuid, const uint32_t reg, + const uint64_t value); + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_MSR_X86_64_H_ */ diff --git a/lib/librte_eal/linuxapp/eal/Makefile b/lib/librte_eal/linuxapp/eal/Makefile index 26eced5..4b6047f 100644 --- a/lib/librte_eal/linuxapp/eal/Makefile +++ b/lib/librte_eal/linuxapp/eal/Makefile @@ -68,6 +68,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_alarm.c ifeq ($(CONFIG_RTE_LIBRTE_IVSHMEM),y) SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_ivshmem.c endif +SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += ./arch/x86/rte_msr.c # from common dir SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_lcore.c diff --git a/lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c b/lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c new file mode 100644 index 0000000..a702b6c --- /dev/null +++ b/lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c @@ -0,0 +1,116 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2016 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include + +#include + +#define CPU_MSR_PATH "/dev/cpu/%u/msr" + +/** + * Function to open CPU's MSR file + */ +static int +__msr_open_file(const unsigned cpuid, int flags) +{ + char fname[PATH_MAX] = {0}; + int fd = -1; + + snprintf(fname, sizeof(fname) - 1, CPU_MSR_PATH, cpuid); + + fd = open(fname, flags); + + if (fd < 0) + RTE_LOG(ERR, EAL, "Error opening file '%s'!\n", fname); + + return fd; +} + +int +rte_msr_read(const unsigned cpuid, const uint32_t reg, uint64_t *value) +{ + int fd = -1; + int ret = -1; + + if (value == NULL) + return -EINVAL; + + fd = __msr_open_file(cpuid, O_RDONLY); + + if (fd >= 0) { + ssize_t read_ret = 0; + + read_ret = pread(fd, value, sizeof(value[0]), (off_t)reg); + + if (read_ret != sizeof(value[0])) { + RTE_LOG(ERR, EAL, "RDMSR failed for reg[0x%x] on CPU lcore %u\n", + (unsigned)reg, cpuid); + } else + ret = 0; + + close(fd); + } + + return ret; +} + +int +rte_msr_write(const unsigned cpuid, const uint32_t reg, const uint64_t value) +{ + int fd = -1; + int ret = -1; + + fd = __msr_open_file(cpuid, O_WRONLY); + + if (fd >= 0) { + ssize_t write_ret = 0; + + write_ret = pwrite(fd, &value, sizeof(value), (off_t)reg); + if (write_ret != sizeof(value)) { + RTE_LOG(ERR, EAL, "WRMSR failed for reg[0x%x] <- value[0x%llx] " + "on CPU lcore %u\n", (unsigned)reg, + (unsigned long long)value, cpuid); + } else + ret = 0; + + close(fd); + } + + return ret; +} -- 1.9.3