From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 81E24C4C0 for ; Thu, 28 Jan 2016 17:48:09 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 28 Jan 2016 08:48:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,359,1449561600"; d="scan'208";a="735983805" Received: from sie-lab-214-241.ir.intel.com (HELO silpixa00382162.ir.intel.com) ([10.237.214.241]) by orsmga003.jf.intel.com with ESMTP; 28 Jan 2016 08:48:07 -0800 From: Deepak Kumar JAIN To: dev@dpdk.org Date: Thu, 28 Jan 2016 17:46:15 +0000 Message-Id: <1454003176-59256-3-git-send-email-deepak.k.jain@intel.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1454003176-59256-1-git-send-email-deepak.k.jain@intel.com> References: <1454003176-59256-1-git-send-email-deepak.k.jain@intel.com> Subject: [dpdk-dev] [PATCH 2/3] qat: add Snow3G UEA2 support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2016 16:48:10 -0000 Added support for wireless Snow3G cipher only, for the Intel Quick Assist device. Signed-off-by: Deepak Kumar JAIN --- doc/guides/cryptodevs/qat.rst | 5 +++-- doc/guides/rel_notes/release_2_3.rst | 1 + drivers/crypto/qat/qat_adf/qat_algs.h | 1 + drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 12 ++++++++++++ drivers/crypto/qat/qat_crypto.c | 8 ++++++++ 5 files changed, 25 insertions(+), 2 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 1901842..eda5de2 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -1,5 +1,5 @@ .. BSD LICENSE - Copyright(c) 2015 Intel Corporation. All rights reserved. + Copyright(c) 2015-2016 Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions @@ -47,6 +47,7 @@ Cipher algorithms: * ``RTE_CRYPTO_SYM_CIPHER_AES128_CBC`` * ``RTE_CRYPTO_SYM_CIPHER_AES192_CBC`` * ``RTE_CRYPTO_SYM_CIPHER_AES256_CBC`` +* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2`` Hash algorithms: @@ -61,7 +62,7 @@ Limitations * Chained mbufs are not supported. * Hash only is not supported. -* Cipher only is not supported. +* Cipher only is not supported except Snow3G UEA2. * Only in-place is currently supported (destination address is the same as source address). * Only supports the session-oriented API implementation (session-less APIs are not supported). * Not performance tuned. diff --git a/doc/guides/rel_notes/release_2_3.rst b/doc/guides/rel_notes/release_2_3.rst index 99de186..0e1f1ff 100644 --- a/doc/guides/rel_notes/release_2_3.rst +++ b/doc/guides/rel_notes/release_2_3.rst @@ -3,6 +3,7 @@ DPDK Release 2.3 New Features ------------ +* **Added the support of Snow3g UEA2 Cipher operation for Intel Quick Assist Devices.* Resolved Issues diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_adf/qat_algs.h index d4aa087..54eeb23 100644 --- a/drivers/crypto/qat/qat_adf/qat_algs.h +++ b/drivers/crypto/qat/qat_adf/qat_algs.h @@ -127,5 +127,6 @@ void qat_alg_ablkcipher_init_dec(struct qat_alg_ablkcipher_cd *cd, unsigned int keylen); int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg); +int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg); #endif diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c index 88fd803..200371d 100644 --- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c +++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c @@ -755,3 +755,15 @@ int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg) } return 0; } + +int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg) +{ + switch (key_len) { + case ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ: + *alg = ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2; + break; + default: + return -EINVAL; + } + return 0; +} diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c index e524638..9ae6715 100644 --- a/drivers/crypto/qat/qat_crypto.c +++ b/drivers/crypto/qat/qat_crypto.c @@ -168,6 +168,14 @@ qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev, } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; break; + case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: + if (qat_alg_validate_snow3g_key(cipher_xform->key.length, + &session->qat_cipher_alg) != 0) { + PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size"); + goto error_out; + } + session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; + break; case RTE_CRYPTO_CIPHER_NULL: case RTE_CRYPTO_CIPHER_3DES_ECB: case RTE_CRYPTO_CIPHER_3DES_CBC: -- 2.1.0