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BY1PR0701MB1723; 5:4D+e8ugd7vI5rUPBrpT36eEIfaQcE23jPfzFEkJc4muFGPLi5EkFQFGFAyt/3u5wf0z6g1eefz9ujSW+63TH/LCYLhARxXR1szllCS8Gvt2xLpL6dNlDmn/x0Wx65mgbGnb2GGIJdMkCqwYjK3G1Ng==; 24:Xz+OWez66QHcx3lY0oeyX3yaO9Brcu6v+H/80syng+oQuRBJUt+V5+2Awc/sykjm0qmMEIRns0cP3Gcr1pQT3GPIN3E5U9TFL/TfDKXKITY= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2016 07:46:28.1925 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1723 Cc: viktorin@rehivetech.com Subject: [dpdk-dev] [PATCH v4 1/4] eal: Introduce new cache line macro definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2016 07:46:32 -0000 - RTE_CACHE_LINE_MIN_SIZE(Supported minimum cache line size) - __rte_cache_min_aligned(Force minimum cache line alignment) - RTE_CACHE_LINE_SIZE_LOG2(Express cache line size in terms of log2) Signed-off-by: Jerin Jacob Suggested-by: Konstantin Ananyev --- lib/librte_eal/common/include/rte_memory.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h index 2200d58..f8dbece 100644 --- a/lib/librte_eal/common/include/rte_memory.h +++ b/lib/librte_eal/common/include/rte_memory.h @@ -74,11 +74,27 @@ enum rte_page_sizes { (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) /**< Return the first cache-aligned value greater or equal to size. */ +/**< Cache line size in terms of log2 */ +#if RTE_CACHE_LINE_SIZE == 64 +#define RTE_CACHE_LINE_SIZE_LOG2 6 +#elif RTE_CACHE_LINE_SIZE == 128 +#define RTE_CACHE_LINE_SIZE_LOG2 7 +#else +#error "Unsupported cache line size" +#endif + +#define RTE_CACHE_LINE_MIN_SIZE 64 /**< Minimum Cache line size. */ + /** * Force alignment to cache line. */ #define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) +/** + * Force minimum cache line alignment. + */ +#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) + typedef uint64_t phys_addr_t; /**< Physical address definition. */ #define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) -- 2.1.0