From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id CE0355A95 for ; Sun, 14 Feb 2016 09:55:30 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 14 Feb 2016 00:55:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,444,1449561600"; d="scan'208";a="745734611" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga003.jf.intel.com with ESMTP; 14 Feb 2016 00:55:29 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id u1E8tR5Q030312; Sun, 14 Feb 2016 16:55:27 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u1E8tP6X028641; Sun, 14 Feb 2016 16:55:27 +0800 Received: (from wenzhuol@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u1E8tPHw028637; Sun, 14 Feb 2016 16:55:25 +0800 From: Wenzhuo Lu To: dev@dpdk.org Date: Sun, 14 Feb 2016 16:55:03 +0800 Message-Id: <1455440106-28547-9-git-send-email-wenzhuo.lu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1455440106-28547-1-git-send-email-wenzhuo.lu@intel.com> References: <1453171693-25571-1-git-send-email-wenzhuo.lu@intel.com> <1455440106-28547-1-git-send-email-wenzhuo.lu@intel.com> Subject: [dpdk-dev] [PATCH v2 08/11] ixgbe/base: set MDIO speed after MAC reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 14 Feb 2016 08:55:31 -0000 The MDIO clock speed must be reconfigured after the MAC reset. The MDIO clock speed becomes invalid, therefore the driver reads invalid PHY register values. The driver now set the MDIO clock speed prior to initializing PHY ops and again after the MAC reset. As now the MDIO speed gets set in more than one place, make a function for it so it will always be done correctly. Signed-off-by: Wenzhuo Lu --- doc/guides/rel_notes/release_16_04.rst | 7 +++++++ drivers/net/ixgbe/base/ixgbe_x550.c | 35 +++++++++++++++++++++++++++------- 2 files changed, 35 insertions(+), 7 deletions(-) diff --git a/doc/guides/rel_notes/release_16_04.rst b/doc/guides/rel_notes/release_16_04.rst index 7687ffd..7ce4547 100644 --- a/doc/guides/rel_notes/release_16_04.rst +++ b/doc/guides/rel_notes/release_16_04.rst @@ -88,6 +88,13 @@ Drivers is already set in ixgbe_set_fdir_drop_queue_82599() which makes more sense for drivers that call that function. +* **ixgbe/base: Set MDIO speed after MAC reset.** + + The MDIO clock speed must be reconfigured after the MAC reset. The MDIO clock + speed becomes invalid, therefore the driver reads invalid PHY register values. + The driver now set the MDIO clock speed prior to initializing PHY ops and + again after the MAC reset. + Libraries ~~~~~~~~~ diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c index 83d9c81..e4416d3 100644 --- a/drivers/net/ixgbe/base/ixgbe_x550.c +++ b/drivers/net/ixgbe/base/ixgbe_x550.c @@ -1679,6 +1679,31 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) } /** + * ixgbe_set_mdio_speed - Set MDIO clock speed + * @hw: pointer to hardware structure + */ +static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) +{ + u32 hlreg0; + + switch (hw->device_id) { + case IXGBE_DEV_ID_X550EM_X_10G_T: + case IXGBE_DEV_ID_X550EM_A_1G_T: + case IXGBE_DEV_ID_X550EM_A_1G_T_L: + case IXGBE_DEV_ID_X550EM_A_10G_T: + case IXGBE_DEV_ID_X550EM_A_SFP: + case IXGBE_DEV_ID_X550EM_A_QSFP: + /* Config MDIO clock speed before the first MDIO PHY access */ + hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); + hlreg0 &= ~IXGBE_HLREG0_MDCSPD; + IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); + break; + default: + break; + } +} + +/** * ixgbe_reset_hw_X550em - Perform hardware reset * @hw: pointer to hardware structure * @@ -1692,7 +1717,6 @@ s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) s32 status; u32 ctrl = 0; u32 i; - u32 hlreg0; bool link_up = false; DEBUGFUNC("ixgbe_reset_hw_X550em"); @@ -1705,12 +1729,7 @@ s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) /* flush pending Tx transactions */ ixgbe_clear_tx_pending(hw); - if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { - /* Config MDIO clock speed before the first MDIO PHY access */ - hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); - hlreg0 &= ~IXGBE_HLREG0_MDCSPD; - IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); - } + ixgbe_set_mdio_speed(hw); /* PHY ops must be identified and initialized prior to reset */ status = hw->phy.ops.init(hw); @@ -1789,6 +1808,8 @@ mac_reset_top: hw->mac.num_rar_entries = 128; hw->mac.ops.init_rx_addrs(hw); + ixgbe_set_mdio_speed(hw); + if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) ixgbe_setup_mux_ctl(hw); -- 1.9.3