From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f51.google.com (mail-pa0-f51.google.com [209.85.220.51]) by dpdk.org (Postfix) with ESMTP id 38158AD89 for ; Wed, 2 Mar 2016 14:59:32 +0100 (CET) Received: by mail-pa0-f51.google.com with SMTP id bj10so64527182pad.2 for ; Wed, 02 Mar 2016 05:59:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=GlowGDjjlbHtT8wVS8UT5DQgQC9eH4npjqID67Xo+Y4=; b=fG5CxxdEBwxyMk9kNXMAu9aLVsKfNjzLhv4SgjnLHf2SxkptKfITFG5L7KRoZM5Ws5 6Du2GHU6OxRAWITu1svuCUSie2C1ssvYl9nSY+cV/Nm1W0W8b85RF8rvsOWj32qARVYV uqCw4TtEyycMInNAd5u1HlkP8Ep2GyzDgEOnpJ0ToZkLIv/H8TIlZ8cuXl6b5Hewo9ql ADBaBtvKN5eBQn5nvvUnzbsDCoSKpdjekmVr1/KTnKZ8CsfYekE7Vduaib+P7XrjEKM4 idnbufh3ZxY8cLxPWwMZlBzbnom2P/nti5eisx8wEWIsmZLfSACv6BNNIEU0zGgCf4zT sajw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=GlowGDjjlbHtT8wVS8UT5DQgQC9eH4npjqID67Xo+Y4=; b=mSeZbjHA7QJGg/6vAZWd4O5t57GvjzHPtH7fZsKmAXOvNOjHMbSKs3ogAYhyg35ojr 5kCeSWR5JOzyv06OreHTaDNLEoM5NquIps0rKXzwnDju+wg6qjJg1qyPOZOfragHuaV1 HlE1fyslEktqGaKtdCfSL/Ie3r7uN9wzApKeO2z/50E5qQjAjVZ0b/yIyz5mdWOEGS77 73HA9FBN0SEwHnh7lF/N/WGsBXnmv+wXtHpwEbQW2S3OeThDWv744xq1VfO8eN8BrQwc 3DunEYWUaMgFMjOoL23QPUnslKZdmmD6i2MG4oaHfMTlpF8JhFss9FEBg3jgzMBAhUxC ikHA== X-Gm-Message-State: AD7BkJJrnW/mGz6hJb6bf8+KE6euLl5ob3GwJjNfHF/CIVZaRZ0lsn+fGDlRQuGmjmd9nQ== X-Received: by 10.66.237.1 with SMTP id uy1mr29355521pac.114.1456927171584; Wed, 02 Mar 2016 05:59:31 -0800 (PST) Received: from user-PC.hsd1.ca.comcast.net (c-24-130-109-45.hsd1.ca.comcast.net. [24.130.109.45]) by smtp.gmail.com with ESMTPSA id to9sm53447895pab.3.2016.03.02.05.59.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 02 Mar 2016 05:59:30 -0800 (PST) From: Ravi Kerur To: dev@dpdk.org Date: Wed, 2 Mar 2016 05:59:34 -0800 Message-Id: <1456927174-30742-1-git-send-email-rkerur@gmail.com> X-Mailer: git-send-email 1.9.1 Subject: [dpdk-dev] [PATCH v1] I217 and I218 changes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Mar 2016 13:59:32 -0000 v1: Make necessary changes to support I217 and I218 NICs. Use v2' incorporating internal review comments as a base. Internal review done by Wenzhuo Lu (Intel) and internal review versions and testing shown below v2': Incorporate Wenzhuo's comments, remove superfluous assignment to fc.requested_mode in em_hardware_init function. Compiled and tested (via testpmd) on Ubuntu 14.04 on target x86_64-native-linuxapp-gcc Compiled for target x86_64-native-linuxapp-clang v1': Modified driver and eal code to support I217 and I218 Intel NICs. Compiled and tested (via testpmd) on Ubuntu 14.04 for target x86_64-native-linuxapp-gcc Compiled for target x86_64-native-linuxapp-clang M. Jay(Intel) had used the patch for DPDK demo. Signed-off-by: Ravi Kerur Acked-by: Wenzhuo Lu --- drivers/net/e1000/base/e1000_osdep.h | 26 +++++++++++++++----- drivers/net/e1000/em_ethdev.c | 32 +++++++++++++++++++++++++ lib/librte_eal/common/include/rte_pci_dev_ids.h | 9 +++++++ 3 files changed, 61 insertions(+), 6 deletions(-) diff --git a/drivers/net/e1000/base/e1000_osdep.h b/drivers/net/e1000/base/e1000_osdep.h index b2c76e3..47a1948 100644 --- a/drivers/net/e1000/base/e1000_osdep.h +++ b/drivers/net/e1000/base/e1000_osdep.h @@ -96,21 +96,35 @@ typedef int bool; #define E1000_PCI_REG(reg) (*((volatile uint32_t *)(reg))) +#define E1000_PCI_REG16(reg) (*((volatile uint16_t *)(reg))) + #define E1000_PCI_REG_WRITE(reg, value) do { \ E1000_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \ } while (0) +#define E1000_PCI_REG_WRITE16(reg, value) do { \ + E1000_PCI_REG16((reg)) = (rte_cpu_to_le_16(value)); \ +} while (0) + #define E1000_PCI_REG_ADDR(hw, reg) \ ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg))) #define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \ E1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2)) -static inline uint32_t e1000_read_addr(volatile void* addr) +#define E1000_PCI_REG_FLASH_ADDR(hw, reg) \ + ((volatile uint32_t *)((char *)(hw)->flash_address + (reg))) + +static inline uint32_t e1000_read_addr(volatile void *addr) { return rte_le_to_cpu_32(E1000_PCI_REG(addr)); } +static inline uint16_t e1000_read_addr16(volatile void *addr) +{ + return rte_le_to_cpu_16(E1000_PCI_REG16(addr)); +} + /* Necessary defines */ #define E1000_MRQC_ENABLE_MASK 0x00000007 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 @@ -155,20 +169,20 @@ static inline uint32_t e1000_read_addr(volatile void* addr) E1000_WRITE_REG(hw, reg, value) /* - * Not implemented. + * Tested on I217/I218 chipset. */ #define E1000_READ_FLASH_REG(hw, reg) \ - (E1000_ACCESS_PANIC(E1000_READ_FLASH_REG, hw, reg, 0), 0) + e1000_read_addr(E1000_PCI_REG_FLASH_ADDR((hw), (reg))) #define E1000_READ_FLASH_REG16(hw, reg) \ - (E1000_ACCESS_PANIC(E1000_READ_FLASH_REG16, hw, reg, 0), 0) + e1000_read_addr16(E1000_PCI_REG_FLASH_ADDR((hw), (reg))) #define E1000_WRITE_FLASH_REG(hw, reg, value) \ - E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG, hw, reg, value) + E1000_PCI_REG_WRITE(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value)) #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ - E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG16, hw, reg, value) + E1000_PCI_REG_WRITE16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value)) #define STATIC static diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c index 4a843fe..a8c26ed 100644 --- a/drivers/net/e1000/em_ethdev.c +++ b/drivers/net/e1000/em_ethdev.c @@ -231,6 +231,32 @@ rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev, return 0; } +/** + * eth_em_dev_is_ich8 - Check for ICH8 device + * @hw: pointer to the HW structure + * + * return TRUE for ICH8, otherwise FALSE + **/ +static bool +eth_em_dev_is_ich8(struct e1000_hw *hw) +{ + DEBUGFUNC("eth_em_dev_is_ich8"); + + switch (hw->device_id) { + case E1000_DEV_ID_PCH_LPT_I217_LM: + case E1000_DEV_ID_PCH_LPT_I217_V: + case E1000_DEV_ID_PCH_LPTLP_I218_LM: + case E1000_DEV_ID_PCH_LPTLP_I218_V: + case E1000_DEV_ID_PCH_I218_V2: + case E1000_DEV_ID_PCH_I218_LM2: + case E1000_DEV_ID_PCH_I218_V3: + case E1000_DEV_ID_PCH_I218_LM3: + return 1; + default: + return 0; + } +} + static int eth_em_dev_init(struct rte_eth_dev *eth_dev) { @@ -265,6 +291,8 @@ eth_em_dev_init(struct rte_eth_dev *eth_dev) adapter->stopped = 0; /* For ICH8 support we'll need to map the flash memory BAR */ + if (eth_em_dev_is_ich8(hw)) + hw->flash_address = (void *)pci_dev->mem_resource[1].addr; if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS || em_hw_init(hw) != 0) { @@ -490,6 +518,7 @@ em_set_pba(struct e1000_hw *hw) break; case e1000_pchlan: case e1000_pch2lan: + case e1000_pch_lpt: pba = E1000_PBA_26K; break; default: @@ -798,6 +827,8 @@ em_hardware_init(struct e1000_hw *hw) hw->fc.low_water = 0x5048; hw->fc.pause_time = 0x0650; hw->fc.refresh_time = 0x0400; + } else if (hw->mac.type == e1000_pch_lpt) { + hw->fc.requested_mode = e1000_fc_full; } diag = e1000_init_hw(hw); @@ -969,6 +1000,7 @@ em_get_max_pktlen(const struct e1000_hw *hw) case e1000_ich9lan: case e1000_ich10lan: case e1000_pch2lan: + case e1000_pch_lpt: case e1000_82574: case e1000_80003es2lan: /* 9K Jumbo Frame size */ case e1000_82583: diff --git a/lib/librte_eal/common/include/rte_pci_dev_ids.h b/lib/librte_eal/common/include/rte_pci_dev_ids.h index d088191..85acaaf 100644 --- a/lib/librte_eal/common/include/rte_pci_dev_ids.h +++ b/lib/librte_eal/common/include/rte_pci_dev_ids.h @@ -310,6 +310,15 @@ RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82573L) RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574L) RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574LA) RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82583V) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPT_I217_LM) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPT_I217_V) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_LM2) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_V2) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_LM3) +RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_V3) + /******************** Physical IGB devices from e1000_hw.h ********************/ -- 1.9.1