From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id B87D64CE7 for ; Fri, 25 Mar 2016 09:42:16 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP; 25 Mar 2016 01:42:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,390,1455004800"; d="scan'208";a="918552652" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga001.jf.intel.com with ESMTP; 25 Mar 2016 01:42:15 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id u2P8gDXf012824; Fri, 25 Mar 2016 16:42:13 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u2P8g9GU021951; Fri, 25 Mar 2016 16:42:11 +0800 Received: (from zhetao@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u2P8g9Ah021947; Fri, 25 Mar 2016 16:42:09 +0800 From: Zhe Tao To: dev@dpdk.org Cc: zhe.tao@intel.com, jingjing.wu@intel.com Date: Fri, 25 Mar 2016 16:42:00 +0800 Message-Id: <1458895321-21896-4-git-send-email-zhe.tao@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1458895321-21896-1-git-send-email-zhe.tao@intel.com> References: <1458816499-705-1-git-send-email-zhe.tao@intel.com> <1458895321-21896-1-git-send-email-zhe.tao@intel.com> Subject: [dpdk-dev] [PATCH 3/3 v7] i40e: Add global reset support for i40e X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Mar 2016 08:42:17 -0000 Add global reset support in i40e. Sometimes the PF reset will fail, and the PF software reset cannot ensure all the status and components are reset. So added the global reset to fix this issue. The essential difference for the new global reset and PF reset is that the PF Reset doesn't clear the packet buffers, doesn't reset the PE firmware, and doesn't bother the other PFs on the chip. Signed-off-by: Zhe Tao --- drivers/net/i40e/i40e_ethdev.c | 35 ++++++++++++++++++++++++++++++++++- drivers/net/i40e/i40e_ethdev.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 87801d3..8336321 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -437,6 +437,8 @@ static int i40e_get_eeprom(struct rte_eth_dev *dev, static void i40e_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr); +static void i40e_do_reset(struct i40e_hw *hw, u32 reset_flags); + static const struct rte_pci_id pci_id_i40e_map[] = { #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)}, #include "rte_pci_dev_ids.h" @@ -836,7 +838,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) ret = i40e_pf_reset(hw); if (ret) { PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret); - return ret; + i40e_do_reset(hw, BIT(__I40E_GLOBAL_RESET_REQUESTED)); } /* Initialize the shared code (base driver) */ @@ -9117,3 +9119,34 @@ static void i40e_set_default_mac_addr(struct rte_eth_dev *dev, /* Flags: 0x3 updates port address */ i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL); } + +/** + * i40e_do_reset - Start a PF or Core Reset sequence + * @pf: board private structure + * @reset_flags: which reset is requested + * + * The essential difference in resets is that the PF Reset + * doesn't clear the packet buffers, doesn't reset the PE + * firmware, and doesn't bother the other PFs on the chip. + **/ +static void i40e_do_reset(struct i40e_hw *hw, u32 reset_flags) +{ + u32 val; + + /* do the biggest reset indicated */ + if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) { + /* Request a Global Reset + * + * This will start the chip's countdown to the actual full + * chip reset event, and a warning interrupt to be sent + * to all PFs, including the requestor. Our handler + * for the warning interrupt will deal with the shutdown + * and recovery of the switch setup. + */ + PMD_INIT_LOG(NOTICE, "GlobalR requested\n"); + val = rd32(hw, I40E_GLGEN_RTRIG); + val |= I40E_GLGEN_RTRIG_GLOBR_MASK; + wr32(hw, I40E_GLGEN_RTRIG, val); + } + /* other reset operations are not supported now */ +} diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index 09fb6e2..f2a2fcc 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -108,6 +108,36 @@ enum i40e_flxpld_layer_idx { I40E_FLXPLD_L4_IDX = 2, I40E_MAX_FLXPLD_LAYER = 3, }; + +/* driver state flags */ +enum i40e_state_t { + __I40E_TESTING, + __I40E_CONFIG_BUSY, + __I40E_CONFIG_DONE, + __I40E_DOWN, + __I40E_NEEDS_RESTART, + __I40E_SERVICE_SCHED, + __I40E_ADMINQ_EVENT_PENDING, + __I40E_MDD_EVENT_PENDING, + __I40E_VFLR_EVENT_PENDING, + __I40E_RESET_RECOVERY_PENDING, + __I40E_RESET_INTR_RECEIVED, + __I40E_REINIT_REQUESTED, + __I40E_PF_RESET_REQUESTED, + __I40E_CORE_RESET_REQUESTED, + __I40E_GLOBAL_RESET_REQUESTED, + __I40E_EMP_RESET_REQUESTED, + __I40E_EMP_RESET_INTR_RECEIVED, + __I40E_FILTER_OVERFLOW_PROMISC, + __I40E_SUSPENDED, + __I40E_BAD_EEPROM, + __I40E_DEBUG_MODE, + __I40E_DOWN_REQUESTED, + __I40E_FD_FLUSH_REQUESTED, + __I40E_RESET_FAILED, + __I40E_PORT_TX_SUSPENDED, + __I40E_VF_DISABLE, +}; #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ -- 2.1.4