From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e28smtp06.in.ibm.com (e28smtp06.in.ibm.com [125.16.236.6]) by dpdk.org (Postfix) with ESMTP id 201F92956 for ; Wed, 30 Mar 2016 17:35:57 +0200 (CEST) Received: from localhost by e28smtp06.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 30 Mar 2016 21:05:56 +0530 Received: from d28relay02.in.ibm.com (9.184.220.59) by e28smtp06.in.ibm.com (192.168.1.136) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Wed, 30 Mar 2016 21:05:53 +0530 X-IBM-Helo: d28relay02.in.ibm.com X-IBM-MailFrom: chaozhu@linux.vnet.ibm.com X-IBM-RcptTo: dev@dpdk.org Received: from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63]) by d28relay02.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u2UFZ4PJ22806986 for ; Wed, 30 Mar 2016 21:05:04 +0530 Received: from d28av01.in.ibm.com (localhost [127.0.0.1]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u2UL4HHX004681 for ; Thu, 31 Mar 2016 02:34:17 +0530 Received: from os_controller.crl.ibm.com ([9.186.57.26]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u2UL4AWq003476 for ; Thu, 31 Mar 2016 02:34:15 +0530 From: Chao Zhu To: dev@dpdk.org Date: Wed, 30 Mar 2016 23:39:17 +0800 Message-Id: <1459352357-852-3-git-send-email-chaozhu@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1459352357-852-1-git-send-email-chaozhu@linux.vnet.ibm.com> References: <1459352357-852-1-git-send-email-chaozhu@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 16033015-0021-0000-0000-00000B34B906 Subject: [dpdk-dev] [PATCH v2 2/2] Fix prefetch instruction on IBM POWER8 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Mar 2016 15:35:58 -0000 Current prefetch instruction (dcbt) implementation for IBM POWER8 has wrong Touch Hint(TH) parameter. The current setting of TH=1 indicates to load data from current cache line and an unlimited number of sequentially following cache lines. TTH=0 means to load data from current cache line. rte_prefetch0 function is defined to load one cache line, which means TH=0 is suited here. Signed-off-by: Chao Zhu --- .../common/include/arch/ppc_64/rte_prefetch.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h b/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h index bcc7185..9a1995e 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h @@ -41,17 +41,17 @@ extern "C" { static inline void rte_prefetch0(const volatile void *p) { - asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p)); + asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p)); } static inline void rte_prefetch1(const volatile void *p) { - asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p)); + asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p)); } static inline void rte_prefetch2(const volatile void *p) { - asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p)); + asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p)); } static inline void rte_prefetch_non_temporal(const volatile void *p) -- 1.7.1