From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id BC9762E81 for ; Fri, 8 Apr 2016 18:20:55 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP; 08 Apr 2016 09:20:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,454,1455004800"; d="scan'208";a="950985353" Received: from dwdohert-dpdk.ir.intel.com ([163.33.210.69]) by orsmga002.jf.intel.com with ESMTP; 08 Apr 2016 09:20:55 -0700 From: Declan Doherty To: dev@dpdk.org Cc: Declan Doherty Date: Fri, 8 Apr 2016 17:17:26 +0100 Message-Id: <1460132247-16553-2-git-send-email-declan.doherty@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1460132247-16553-1-git-send-email-declan.doherty@intel.com> References: <1460132247-16553-1-git-send-email-declan.doherty@intel.com> Subject: [dpdk-dev] [PATCH 1/2] docs: add cryptodevs guide overview section X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Apr 2016 16:20:56 -0000 Details supported device features and algorithms for each crypto PMD. Signed-off-by: Declan Doherty --- doc/guides/cryptodevs/index.rst | 3 +- doc/guides/cryptodevs/overview.rst | 94 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 doc/guides/cryptodevs/overview.rst diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst index 85193da..a3f11f3 100644 --- a/doc/guides/cryptodevs/index.rst +++ b/doc/guides/cryptodevs/index.rst @@ -35,8 +35,9 @@ Crypto Device Drivers :maxdepth: 2 :numbered: + overview aesni_mb aesni_gcm null snow3g - qat + qat \ No newline at end of file diff --git a/doc/guides/cryptodevs/overview.rst b/doc/guides/cryptodevs/overview.rst new file mode 100644 index 0000000..9f9af43 --- /dev/null +++ b/doc/guides/cryptodevs/overview.rst @@ -0,0 +1,94 @@ +.. BSD LICENSE + Copyright(c) 2016 Intel Corporation. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +Crypto Device Supported Functionality Matrices +---------------------------------------------- + +Supported Feature Flags + +.. csv-table:: + :header: "Feature Flags", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g" + :stub-columns: 1 + + "RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO",x,x,,, + "RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO",,,,, + "RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING",x,x,x,x,x + "RTE_CRYPTODEV_FF_CPU_SSE",,,x,x,x + "RTE_CRYPTODEV_FF_CPU_AVX",,,x,x,x + "RTE_CRYPTODEV_FF_CPU_AVX2",,,x,x, + "RTE_CRYPTODEV_FF_CPU_AESNI",,,x,x, + "RTE_CRYPTODEV_FF_HW_ACCELERATED",x,,,, + +Supported Cipher Algorithms + +.. csv-table:: + :header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g" + :stub-columns: 1 + + "NULL",,x,,, + "AES_CBC_128",x,,x,, + "AES_CBC_192",x,,x,, + "AES_CBC_256",x,,x,, + "AES_CTR_128",,,,, + "AES_CTR_192",,,,, + "AES_CTR_256",,,,, + "SNOW3G_UEA2",x,,,,x + +Supported Authentication Algorithms + +.. csv-table:: + :header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g" + :stub-columns: 1 + + "NONE",,x,,, + "MD5",,,,, + "MD5_HMAC",,,x,, + "SHA1",,,,, + "SHA1_HMAC",x,,x,, + "SHA224",,,,, + "SHA224_HMAC",,,x,, + "SHA256",,,,, + "SHA256_HMAC",x,,x,, + "SHA384",,,,, + "SHA384_HMAC",,,x,, + "SHA512",,,,, + "SHA512_HMAC",x,,x,, + "AES_XCBC",x,,x,, + "SNOW3G_UIA2",x,,,,x + + +Supported AEAD Algorithms + +.. csv-table:: + :header: "AEAD Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g" + :stub-columns: 1 + + "AES_GCM_128",x,,x,, + "AES_GCM_192",x,,,, + "AES_GCM_256",x,,,, -- 2.5.5